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Intel(R) 925X Express Chipset
Datasheet For the Intel(R) 82925X Memory Controller Hub (MCH)
August 2004
www..com Document Number: 301464-002
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL(R) PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel(R) 82925X MCH may contain design defects or errors known as errata, which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Intel and Pentium are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others.
(c) Copyright 2004, Intel Corporation
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Contents
1 Introduction ........................................................................................................................13 1.1 1.2 1.3 Terminology ..........................................................................................................15 Reference Documents ..........................................................................................17 MCH Overview......................................................................................................17 1.3.1 Host Interface ........................................................................................17 1.3.2 System Memory Interface .....................................................................18 1.3.3 Direct Media Interface (DMI) .................................................................19 1.3.4 PCI Express* Graphics Interface ..........................................................19 1.3.5 System Interrupts ..................................................................................20 1.3.6 MCH Clocking .......................................................................................21 1.3.7 Power Management ..............................................................................21 Host Interface Signals...........................................................................................24 DDR2 DRAM Channel A Interface........................................................................27 DDR2 DRAM Channel B Interface........................................................................28 DDR2 DRAM Reference and Compensation........................................................29 PCI Express* x16 Graphics Port Signals ..............................................................29 Clocks, Reset, and Miscellaneous ........................................................................30 Direct Media Interface (DMI).................................................................................30 Power and Ground................................................................................................31 Reset States and Pull-up/Pull-downs....................................................................31
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Signal Description..............................................................................................................22 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
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Register Description ..........................................................................................................36 3.1 3.2 3.3 Register Terminology............................................................................................36 Platform Configuration ..........................................................................................38 General Routing Configuration Accesses .............................................................39 3.3.1 Standard PCI Bus Configuration Mechanism........................................39 3.3.2 Logical PCI Bus 0 Configuration Mechanism ........................................40 3.3.3 Primary PCI and Downstream Configuration Mechanism .....................40 3.3.4 PCI Express* Enhanced Configuration Mechanism ..............................41 (R) 3.3.5 Intel 82925X MCH Configuration Cycle Flowchart ..............................43 I/O Mapped Registers ...........................................................................................44 3.4.1 CONFIG_ADDRESS--Configuration Address Register .......................44 3.4.2 CONFIG_DATA--Configuration Data Register.....................................45 Device 0 Function 0 PCI Configuration Register Details ......................................49 4.1.1 VID--Vendor Identification (D0:F0).......................................................49 4.1.2 DID--Device Identification (D0:F0) .......................................................49 4.1.3 PCICMD--PCI Command (D0:F0)........................................................50 4.1.4 PCISTS--PCI Status (D0:F0) ...............................................................51 4.1.5 RID--Revision Identification (D0:F0) ....................................................52 4.1.6 CC--Class Code (D0:F0)......................................................................52 4.1.7 MLT--Master Latency Timer (D0:F0) ...................................................53
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Host Bridge/DRAM Controller Registers (D0:F0) ..............................................................46 4.1
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4.1.8 4.1.9 4.1.10 4.1.11 4.1.12 4.1.13 4.1.14 4.1.15 4.1.16 4.1.17 4.1.18 4.1.19 4.1.20 4.1.21 4.1.22 4.1.23 4.1.24 4.1.25 4.1.26 4.1.27 4.1.28 4.1.29 4.1.30 4.1.31 4.1.32 4.1.33 4.1.34 4.1.35 4.1.36 5 5.1
HDR--Header Type (D0:F0) .................................................................53 SVID--Subsystem Vendor Identification (D0:F0)..................................53 SID--Subsystem Identification (D0:F0).................................................54 CAPPTR--Capabilities Pointer (D0:F0) ................................................54 EPBAR--Egress Port Base Address (D0:F0) .......................................55 MCHBAR--MCH Memory Mapped Register Range Base Address (D0:F0) ..................................................................................................56 PCIEXBAR--PCI Express* Register Range Base Address (D0:F0) ....57 DMIBAR--Root Complex Register Range Base Address (D0:F0) .......58 DEVEN--Device Enable (D0:F0) ..........................................................59 DEAP--DRAM Error Address Pointer (D0:F0)......................................60 DERRSYN--DRAM Error Syndrome (D0:F0) .......................................61 DERRDST--DRAM Error Destination (D0:F0)......................................62 PAM0--Programmable Attribute Map 0 (D0:F0)...................................63 PAM1--Programmable Attribute Map 1 (D0:F0)...................................64 PAM2--Programmable Attribute Map 2 (D0:F0)...................................65 PAM3--Programmable Attribute Map 3 (D0:F0)...................................66 PAM4--Programmable Attribute Map 4 (D0:F0)...................................67 PAM5--Programmable Attribute Map 5 (D0:F0)...................................68 PAM6--Programmable Attribute Map 6 (D0:F0)...................................69 LAC--Legacy Access Control (D0:F0)..................................................70 TOLUD--Top of Low Usable DRAM (D0:F0)........................................71 SMRAM--System Management RAM Control (D0:F0).........................72 ESMRAMC--Extended System Management RAM Control (D0:F0) ...73 ERRSTS--Error Status (D0:F0)............................................................73 ERRCMD--Error Command (D0:F0) ....................................................75 SMICMD--SMI Command (D0:F0) .......................................................76 SCICMD--SCI Command (D0:F0)........................................................77 SKPD--Scratchpad Data (D0:F0) .........................................................77 CAPID0--Capability Identifier (D0:F0) ..................................................78
MCHBAR Registers ...........................................................................................................80 MCHBAR Register Details ....................................................................................81 5.1.1 C0DRB0--Channel A DRAM Rank Boundary Address 0 .....................81 5.1.2 C0DRB1--Channel A DRAM Rank Boundary Address 1 .....................83 5.1.3 C0DRB2--Channel A DRAM Rank Boundary Address 2 .....................83 5.1.4 C0DRB3--Channel A DRAM Rank Boundary Address 3 .....................83 5.1.5 C0DRA0--Channel A DRAM Rank 0,1 Attribute ..................................84 5.1.6 C0DRA2--Channel A DRAM Rank 2,3 Attribute ..................................84 5.1.7 C0DCLKDIS--Channel A DRAM Clock Disable ...................................85 5.1.8 C0BNKARC--Channel A DRAM Bank Architecture .............................86 5.1.9 C0DRT1--Channel A DRAM Timing Register ......................................87 5.1.10 C0DRC0--Channel A DRAM Controller Mode 0 ..................................89 5.1.11 C1DRB0--Channel B DRAM Rank Boundary Address 0 .....................91 5.1.12 C1DRB1--Channel B DRAM Rank Boundary Address 1 .....................91 5.1.13 C1DRB2--Channel B DRAM Rank Boundary Address 2 .....................91 5.1.14 C1DRB3--Channel B DRAM Rank Boundary Address 3 .....................91 5.1.15 C1DRA0--Channel B DRAM Rank 0,1 Attribute ..................................91 5.1.16 C1DRA2--Channel B DRAM Rank 2,3 Attribute ..................................92 5.1.17 C1DCLKDIS--Channel B DRAM Clock Disable ...................................92 5.1.18 C1BNKARC--Channel B Bank Architecture .........................................92 5.1.19 C1DRT1--Channel B DRAM Timing Register 1 ...................................92 5.1.20 C1DRC0--Channel B DRAM Controller Mode 0 ..................................92 5.1.21 PMCFG--Power Management Configuration .......................................93
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PMSTS--Power Management Status ...................................................93
EPBAR Registers--Egress Port Register Summary.........................................................94 EP RCRB Configuration Register Details .............................................................94 6.1.1 EPESD--EP Element Self Description .................................................95 6.1.2 EPLE1D--EP Link Entry 1 Description .................................................96 6.1.3 EPLE1A--EP Link Entry 1 Address ......................................................96 6.1.4 EPLE2D--EP Link Entry 2 Description .................................................97 6.1.5 EPLE2A--EP Link Entry 2 Address ......................................................98 Direct Media Interface (DMI) RCRB Register Details .........................................101 7.1.1 DMIVCECH--DMI Virtual Channel Enhanced Capability Header.......101 7.1.2 DMIPVCCAP1--DMI Port VC Capability Register 1 ...........................101 7.1.3 DMIPVCCAP2--DMI Port VC Capability Register 2 ...........................102 7.1.4 DMIPVCCTL--DMI Port VC Control ...................................................102 7.1.5 DMIVC0RCAP--DMI VC0 Resource Capability..................................103 7.1.6 DMIVC0RCTL0--DMI VC0 Resource Control ....................................104 7.1.7 DMIVC0RSTS--DMI VC0 Resource Status .......................................105 7.1.8 DMIVC1RCAP--DMI VC1 Resource Capability..................................105 7.1.9 DMIVC1RCTL1--DMI VC1 Resource Control ....................................106 7.1.10 DMIVC1RSTS--DMI VC1 Resource Status .......................................107 7.1.11 DMILCAP--DMI Link Capabilities .......................................................107 7.1.12 DMILCTL--DMI Link Control...............................................................108 7.1.13 DMILSTS--DMI Link Status................................................................108 Device 1 Configuration Register Details .............................................................113 8.1.1 VID1--Vendor Identification (D1:F0)...................................................113 8.1.2 DID1--Device Identification (D1:F0) ...................................................113 8.1.3 PCICMD1--PCI Command (D1:F0)....................................................114 8.1.4 PCISTS1--PCI Status (D1:F0) ...........................................................115 8.1.5 RID1--Revision Identification (D1:F0) ................................................117 8.1.6 CC1--Class Code (D1:F0)..................................................................117 8.1.7 CL1--Cache Line Size (D1:F0) ...........................................................118 8.1.8 HDR1--Header Type (D1:F0) .............................................................118 8.1.9 PBUSN1--Primary Bus Number (D1:F0)............................................118 8.1.10 SBUSN1--Secondary Bus Number (D1:F0) .......................................119 8.1.11 SUBUSN1--Subordinate Bus Number (D1:F0) ..................................119 8.1.12 IOBASE1--I/O Base Address (D1:F0) ................................................120 8.1.13 IOLIMIT1--I/O Limit Address (D1:F0).................................................120 8.1.14 SSTS1--Secondary Status (D1:F0) ....................................................121 8.1.15 MBASE1--Memory Base Address (D1:F0).........................................122 8.1.16 MLIMIT1--Memory Limit Address (D1:F0) .........................................123 8.1.17 PMBASE1--Prefetchable Memory Base Address (D1:F0) .................124 8.1.18 PMLIMIT1--Prefetchable Memory Limit Address (D1:F0)..................125 8.1.19 CAPPTR1--Capabilities Pointer (D1:F0) ............................................125 8.1.20 INTRLINE1--Interrupt Line (D1:F0) ....................................................126 8.1.21 INTRPIN1--Interrupt Pin (D1:F0)........................................................126 8.1.22 BCTRL1--Bridge Control (D1:F0).......................................................127 8.1.23 PM_CAPID1--Power Management Capabilities (D1:F0) ...................129 8.1.24 PM_CS1--Power Management Control/Status (D1:F0) .....................130 8.1.25 SS_CAPID--Subsystem ID and Vendor ID Capabilities (D1:F0)........131 8.1.26 SS--Subsystem ID and Subsystem Vendor ID (D1:F0) .....................131
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DMIBAR Registers--Direct Media Interface (DMI) RCRB ..............................................100 7.1
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Host-PCI Express* Graphics Bridge Registers (D1:F0) ..................................................110 8.1
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8.1.27 8.1.28 8.1.29 8.1.30 8.1.31 8.1.32 8.1.33 8.1.34 8.1.35 8.1.36 8.1.37 8.1.38 8.1.39 8.1.40 8.1.41 8.1.42 8.1.43 8.1.44 8.1.45 8.1.46 8.1.47 8.1.48 8.1.49 8.1.50 8.1.51 8.1.52 8.1.53 8.1.54 8.1.55 8.1.56 8.1.57 8.1.58 8.1.59 9 9.1
MSI_CAPID--Message Signaled Interrupts Capability ID (D1:F0) .....132 MC--Message Control (D1:F0)...........................................................133 MA--Message Address (D1:F0) .........................................................134 MD--Message Data (D1:F0)...............................................................134 PEG_CAPL--PCI Express* Capability List (D1:F0) ............................135 PEG_CAP--PCI Express*-G Capabilities (D1:F0)..............................135 DCAP--Device Capabilities (D1:F0) ...................................................136 DCTL--Device Control (D1:F0)...........................................................137 DSTS--Device Status (D1:F0)............................................................138 LCAP--Link Capabilities (D1:F0) ........................................................139 LCTL--Link Control (D1:F0)................................................................140 LSTS--Link Status (D1:F0).................................................................141 SLOTCAP--Slot Capabilities (D1:F0) .................................................142 SLOTCTL--Slot Control (D1:F0).........................................................143 SLOTSTS--Slot Status (D1:F0)..........................................................144 RCTL--Root Control (D1:F0) ..............................................................145 RSTS--Root Status (D1:F0) ...............................................................146 PEGLC--PCI Express*-G Legacy Control ..........................................147 VCECH--Virtual Channel Enhanced Capability Header (D1:F0)........148 PVCCAP1--Port VC Capability Register 1 (D1:F0) ............................148 PVCCAP2--Port VC Capability Register 2 (D1:F0) ............................149 PVCCTL--Port VC Control (D1:F0) ....................................................149 VC0RCAP--VC0 Resource Capability (D1:F0)...................................150 VC0RCTL--VC0 Resource Control (D1:F0) .......................................150 VC0RSTS--VC0 Resource Status (D1:F0) ........................................151 VC1RCAP--VC1 Resource Capability (D1:F0)...................................151 VC1RCTL--VC1 Resource Control (D1:F0) .......................................152 VC1RSTS--VC1 Resource Status (D1:F0) ........................................153 RCLDECH--Root Complex Link Declaration Enhanced Capability Header (D1:F0) ...................................................................................153 ESD--Element Self Description (D1:F0).............................................154 LE1D--Link Entry 1 Description (D1:F0).............................................155 LE1A--Link Entry 1 Address (D1:F0)..................................................156 PEGSSTS--PCI Express*-G Sequence Status (D1:F0).....................156
System Address Map.......................................................................................................158 Legacy Address Range.......................................................................................159 9.1.1 DOS Range (0h - 9_FFFFh)...............................................................160 9.1.2 Legacy Video Area (A_0000h-B_FFFFh) ...........................................160 9.1.3 Expansion Area (C_0000h-D_FFFFh)................................................161 9.1.4 Extended System BIOS Area (E_0000h-E_FFFFh) ...........................162 9.1.5 System BIOS Area (F_0000h-F_FFFFh)............................................162 9.1.6 Programmable Attribute Map (PAM) Memory Area Details.................162 Main Memory Address Range (1 MB to TOLUD) ...............................................163 9.2.1 ISA Hole (15 MB-16 MB) ....................................................................163 9.2.2 TSEG...................................................................................................164 9.2.3 Pre-allocated Memory .........................................................................164 PCI Memory Address Range (TOLUD - 4 GB) ..................................................164 9.3.1 APIC Configuration Space (FEC0_0000h-FECF_FFFFh) ..................165 9.3.2 HSEG (FEDA_0000h-FEDB_FFFFh).................................................166 9.3.3 FSB Interrupt Memory Space (FEE0_0000-FEEF_FFFF) .................166 9.3.4 High BIOS Area ...................................................................................166 9.3.5 PCI Express* Configuration Address Space .......................................166
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9.3
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9.3.6 PCI Express* Graphics Attach ............................................................167 9.3.7 AGP DRAM Graphics Aperture ...........................................................167 System Management Mode (SMM) ....................................................................168 9.4.1 SMM Space Definition .........................................................................168 9.4.2 SMM Space Restrictions .....................................................................169 9.4.3 SMM Space Combinations..................................................................169 9.4.4 SMM Control Combinations ................................................................170 9.4.5 SMM Space Decode and Transaction Handling .................................170 9.4.6 Processor WB Transaction to an Enabled SMM Address Space .......170 9.4.7 SMM Access through GTT TLB ..........................................................171 9.4.8 Memory Shadowing.............................................................................171 9.4.9 I/O Address Space ..............................................................................171 9.4.10 PCI Express* I/O Address Mapping ....................................................172 9.4.11 MCH Decode Rules and Cross-Bridge Address Mapping...................172 9.4.12 Legacy VGA and I/O Range Decode Rules ........................................172 Host Interface......................................................................................................174 10.1.1 FSB GTL+ Termination .......................................................................174 10.1.2 FSB Dynamic Bus Inversion................................................................174 10.1.3 APIC Cluster Mode Support ................................................................175 System Memory Controller .................................................................................175 10.2.1 Memory Organization Modes ..............................................................175 System Memory Configuration Register Overview .............................................177 10.3.1 DRAM Technologies and Organization ...............................................178 10.3.1.1 Rules for Populating DIMM Slots .......................................178 10.3.1.2 System Memory Supported Configurations .......................179 10.3.1.3 Main Memory DRAM Address Translation and Decoding .179 10.3.2 DRAM Clock Generation .....................................................................182 10.3.3 Suspend to RAM and Resume............................................................182 10.3.4 DDR2 On-Die Termination ..................................................................182 10.3.5 DDR2 Off-Chip Driver Impedance Calibration ....................................182 PCI Express*.......................................................................................................183 10.4.1 Transaction Layer................................................................................183 10.4.2 Data Link Layer ...................................................................................183 10.4.3 Physical Layer .....................................................................................183 Power Management............................................................................................184 Clocking ..............................................................................................................184
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Functional Description .....................................................................................................174 10.1
10.2 10.3
10.4
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Electrical Characteristics .................................................................................................186 11.1 11.2 11.3 11.4 Absolute Maximum Ratings ................................................................................186 Power Characteristics .........................................................................................187 Signal Groups .....................................................................................................188 General DC Characteristics ................................................................................190
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Ballout and Package Information.....................................................................................194 12.1 12.2 Ballout .................................................................................................................194 Package Information...........................................................................................220
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Testability.........................................................................................................................222 13.1 13.2 Complimentary Pins............................................................................................222 XOR Test Mode Initialization ..............................................................................223
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XOR Chain Definition..........................................................................................223 XOR Chains ........................................................................................................223 Pads Excluded from XOR Mode(s).....................................................................243
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Figures
Figure 1-1. Intel(R) 925X Express Chipset System Block Diagram Example ......................14 (R) Figure 2-1. Intel MCH Signal Interface Diagram ..............................................................23 (R) Figure 3-1. Conceptual Intel 925X Express Chipset Platform PCI Configuration Diagram ......................................................................................................................38 Figure 3-2. DMI Type 0 Configuration Address Translation ..............................................40 Figure 3-3. DMI Type 1 Configuration Address Translation ..............................................41 Figure 3-4. Memory Map to PCI Express* Device Configuration Space ...........................42 (R) Figure 3-5. Intel 82925X MCH Configuration Cycle Flowchart ........................................43 Figure 6-1. Link Declaration Topology...............................................................................94 Figure 9-1. System Address Ranges...............................................................................159 Figure 9-2. Microsoft MS-DOS* Legacy Address Range ................................................160 Figure 9-3. Main Memory Address Range.......................................................................163 Figure 9-4. PCI Memory Address Range ........................................................................165 Figure 10-1. System Memory Styles................................................................................176 Figure 10-2. System Clocking Example ..........................................................................185 (R) Figure 12-1. Intel 82925X MCH Ballout (Top View: Left Side).......................................195 (R) Figure 12-2. Intel 82925X MCH Ballout (Top View: Right Side) ....................................196 Figure 12-3. MCH Package Dimensions .........................................................................221
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Tables
Table 2-1. Host Interface Reset and S3 States .................................................................32 Table 2-2. System Memory Reset and S3 States .............................................................33 Table 2-3. PCI Express* Graphics x16 Port Reset and S3 States ....................................34 Table 2-4. DMI Reset and S3 States .................................................................................34 Table 2-5. Clocking Reset and S3 States..........................................................................35 Table 2-6. Miscellaneous Reset and S3 States.................................................................35 Table 3-1. Device Number Assignment for Internal MCH Devices ...................................39 Table 4-1. Device 0 Function 0 Register Address Map Summary.....................................46 Table 6-1. Egress Port Register Address Map ..................................................................94 Table 7-1. DMI Register Address Map Summary............................................................100 Table 8-1. Host-PCI Express* Graphics Bridge Register Address Map (D1:F0).............110 Table 9-1. Expansion Area Memory Segments...............................................................161 Table 9-2. Extended System BIOS Area Memory Segments..........................................162 Table 9-3. System BIOS Area Memory Segments ..........................................................162 Table 9-4. Pre-Allocated Memory Example for 64-MB DRAM and 1-MB TSEG .............164 Table 9-5. SMM Space Table..........................................................................................169 Table 9-6. SMM Control Table ........................................................................................170 Table 10-1. Sample System Memory Organization with Interleaved Channels...............176 Table 10-2. Sample System Memory Organization with Asymmetric Channels .............176 Table 10-3. DDR2 DIMM Supported Configurations .......................................................179 Table 10-4. DRAM Address Translation (Single Channel/Dual Asymmetric Mode)........180 Table 10-5. DRAM Address Translation (Dual Channel Symmetric Mode) ....................181 Table 11-1. Absolute Maximum Ratings..........................................................................186 Table 11-2. Non-Memory Power Characteristics.............................................................187 Table 11-3. DDR2 Power Characteristics........................................................................187 Table 11-4. Signal Groups...............................................................................................188 Table 11-5. DC Characteristics .......................................................................................190 Table 12-1. MCH Ballout Sorted By Signal Name ...........................................................197 Table 12-2. MCH Ballout Sorted By Ball Number............................................................208 Table 13-1. Complimentary Pins to Drive........................................................................222 Table 13-2. XOR Chain Outputs......................................................................................223 Table 13-3. XOR Chain #0 ..............................................................................................224 Table 13-4. XOR Chain #1 ..............................................................................................226 Table 13-5. XOR Chain #2 ..............................................................................................228 Table 13-6. XOR Chain #3 ..............................................................................................230 Table 13-7. XOR Chain #4 ..............................................................................................232 Table 13-8. XOR Chain #5 ..............................................................................................234 Table 13-9. XOR Chain #6 ..............................................................................................236 Table 13-10. XOR Chain #7 ............................................................................................238 Table 13-11. XOR Chain #8 ............................................................................................240 Table 13-12. XOR Chain #9 ............................................................................................242 Table 13-13. XOR Pad Exclusion List .............................................................................243
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Revision History
Revision -001 -002 * Initial Release * Added EM64T Support Information Description Date June 2004 August 2004
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Intel(R) 82925X MCH Features
Processor Interface One Intel(R) Pentium(R) 4 processor (supports 775-land package) Supports Pentium 4 processor FSB interrupt delivery 800 MT/s (200 MHz) FSB Supports Hyper-Threading Technology (HT Technology) FSB Dynamic Bus Inversion (DBI) 32-bit host bus addressing for access to 4 GB of memory space 12-deep In-Order Queue 1-deep Defer Queue GTL+ bus driver with integrated GTL termination resistors Supports a Cache Line Size of 64 bytes Supports Intel Pentium(R) 4 processors with Intel(R) EM64T DMI Interface A chip-to-chip connection interface to Intel(R) ICH6 2 GB/s point-to-point DMI to ICH6 (1 GB/s each direction) 100 MHz reference clock (shared with PCI Express Graphics Attach). 32-bit downstream addressing Messaging and Error Handling System Memory One or two 64-bit wide DDR2 SDRAM data channels Bandwidth up to 8.5 GB/s (DDR2 533) in dual-channel Interleaved mode ECC and Non-ECC memory 256-Mb, 512-Mb and 1-Gb DDR2 technologies Only x8, x16, DDR2 devices with four banks and also supports eight bank, 1-Gbit DDR2 devices. Opportunistic refresh Up to 64 simultaneously open pages (four ranks of eight bank devices* 2 channels) SPD (Serial Presence Detect) scheme for DIMM detection support Suspend-to-RAM support using CKE Supports configurations defined in the JEDEC DDR2 DIMM specification only PCI Express Graphics Interface One x16 PCI Express port Compatible with the PCI Express Base Specification Revision 1.0a Package 37.5 mm x 37.5 mm., 1210 balls, variable ball pitch
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Intel 82925X MCH Datasheet
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Introduction
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Introduction
The Intel(R) 925X Express chipset is designed for use with the Intel(R) Pentium(R) 4 processor in entrylevel, uniprocessor workstation platforms. The chipset contains two components: 82925X Memory Controller Hub (MCH) for the host bridge and I/O Controller Hub 6 (ICH6) for the I/O subsystem. The MCH provides the interface to the processor, main memory, PCI Express, and the ICH6. The ICH6 is the sixth generation I/O Controller Hub and provides a multitude of I/O related functions. Figure 1-1 shows an example system block diagram for the 925X Express chipset. For great workstation application flexibility, the Intel(R) 925X Express chipset is specifically designed to support Intel(R) Extended Memory 64 Technology* (Intel(R) EM64T) enabling 64-bit memory addressability. Select versions of the Pentium 4 processor support Intel(R) Extended Memory 64 Technology* (Intel(R) EM64T) as an enhancement to Intel's IA-32 architecture on workstation platforms. This enhancement enables the processor to execute operating systems and applications written to take advantage of Intel(R) EM64T. Further details on the 64-bit extension architecture and programming model can be found in the Intel(R) Extended Memory 64 Technology Software Developer Guide at http://developer.intel.com/technology/64bitextensions/.
* Intel(R) Extended Memory 64 Technology (Intel(R) EM64T) requires a computer system with a processor, chipset, BIOS, OS, device drivers and applications enabled for Intel EM64T. Processor will not operate (including 32-bit operation) without an Intel EM64T-enabled BIOS. Performance will vary depending on your hardware and software configurations. Intel EM64T-enabled OS, BIOS, device drivers and applications may not be available. Check with your vendor for more information.
This document is the datasheet for the Intel(R) 82925X MCH. Topics covered include; signal description, system memory map, register descriptions, a description of the MCH interfaces and major functional units, electrical characteristics, ballout definitions, and package characteristics. Note: Unless otherwise specified, ICH6 refers to the Intel(R) 82801FB ICH6, 82801FR ICHR, 82801FW ICH6W, and 82801FRW ICH6RW I/O Controller Hub components.
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Figure 1-1. Intel(R) 925X Express Chipset System Block Diagram Example
Intel(R) Pentium(R) 4 Processor 200 MHz FSB (800 MT/s)
Intel(R) 925X Express Chipset
System Memory DDR2 Channel A Display Graphics Card PCI Express x16 Graphics Intel(R) 82925X MCH DDR2
Channel B
DDR2
DDR2
DMI Interface USB 2.0 8 ports, 480 Mb/s IDE 4 SATA Ports 150 MB/s Intel(R) ICH6 Family AC '97/Intel(R) High Definition Audio CODECs PCI Express* x1 Intel(R) PCI Express Gigabit Ethernet GPIO Seven PCI Masters PCI Bus System Management (TCO) SMBus 2.0/I2C
Power Management Clock Generation LAN Connect/ASF
Flash BIOS
LPC Interface
SIO
Sys_Blk_P
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1.1
Terminology
Term Core DBI DDR2 DMI FSB Full Reset Host INTx Intel(R) ICH6 Description Core refers to the internal base logic in the MCH. Dynamic Bus Inversion. A second generation Double Data Rate SDRAM memory technology. The Direct Media Interface is the connection between the MCH and the Intel(R) ICH6. Front Side Bus. The FSB is synonymous with Host or processor bus Full reset is when PWROK is de-asserted. Warm reset is when both RSTIN# and PWROK are asserted. This term is used synonymously with processor. An interrupt request signal where X stands for interrupts A,B,C and D. Sixth generation I/O Controller Hub component that contains additional functionality compared to previous ICH6s. The Intel(R) I/O Controller Hub component contains the primary PCI interface, LPC interface, USB2, ATA-100, and other I/O functions. It communicates with the MCH over a proprietary interconnect called DMI. The Memory Controller Hub (MCH) component contains the processor interface and DRAM controller. It may also contain an x16 PCI Express port (typically the external graphics interface). It communicates with the I/O controller hub (ICH6*) and other I/O controller hubs over the DMI interconnect. Message Signaled Interrupt. A transaction initiated outside the host, conveying interrupt information to the receiving agent through the same path that normally carries read and write commands. Third Generation Input Output (PCI Express) Graphics Attach called PCI Express Graphics. A high-speed serial interface whose configuration is software compatible with the existing PCI specifications. The specific PCI Express implementation intended for connecting the MCH to an external graphics controller is a x16 link and replaces AGP. The physical PCI bus that is driven directly by the ICH6 component. Communication between Primary PCI and the MCH occurs over DMI. Note that the Primary PCI bus is not PCI Bus 0 from a configuration standpoint. System Control Interrupt. SCI is used in ACPI protocol. An indication that an unrecoverable error has occurred on an I/O bus. System Management Interrupt. SMI is used to indicate any of several system conditions (such as thermal sensor events, throttling activated, access to System Management RAM, chassis open, or other system state related activity). A unit of DRAM corresponding to eight x8 SDRAM devices in parallel or four x16 SDRAM devices in parallel, ignoring ECC. These devices are usually, but not always, mounted on a single side of a DIMM. Top Of Low Memory. The highest address below 4 GB for which a processor-initiated memory read or write transaction will create a corresponding cycle to DRAM on the memory interface.
MCH
MSI
PCI Express*
Primary PCI
SCI SERR SMI
Rank
TOLM
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Term VCO Voltage Controlled Oscillator.
Description
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1.2
Reference Documents
Document Title Intel(R) 925X Express Chipset Thermal Design Guide Document Number/Location http://intel.com/design/ chipsets/designex/ 301466.htm http://intel.com/design/ chipsets/datashts/ 301473.htm http://www.acpi.info/ http://www.acpi.info/ http://www.pcisig.com/specif ications http://www.pcisig.com/specif ications
Intel(R) I/O Controller Hub 6 (ICH6) Family Datasheet
Advanced Configuration and Power Interface Specification, Version 2.0 Advanced Configuration and Power Interface Specification, Version 1.0b The PCI Local Bus Specification, Version 2.3 PCI Express* Specification, Version 1.0a
1.3
MCH Overview
The MCH connects to the processor as shown in Figure 1-1. A major role of the MCH in a system is to manage the flow of information between its interfaces: the processor interface (FSB), the System Memory interface (DRAM controller), the external graphics interface via PCI Express, and the I/O Controller Hub through the DMI interface. This includes arbitrating between the interfaces when each initiates transactions. The processor interface supports the Pentium 4 processor subset of the Extended Mode of the Scalable Bus Protocol. The MCH supports one or two channels of DDR2 SDRAM. The MCH also supports the new PCI Express based external graphics attach. Thus, the 925X Express chipset is NOT compatible with AGP (1X, 2X, 4X, or 8X). To increase system performance, the MCH incorporates several queues and a write cache. The MCH also contains advanced desktop power management logic.
1.3.1
Host Interface
The MCH is optimized for the Pentium 4 processors in the LGA775 socket. The MCH supports a FSB frequency of 200 MHz (800 MT/s) using a scalable FSB. The MCH supports the Pentium 4 processor subset of the Extended Mode Scaleable Bus Protocol. The primary enhancements over the Compatible Mode P6 bus protocol are: Source synchronous double-pumped (2) Address and Source synchronous quad-pumped (4x) Data. The MCH supports 32-bit host addressing, decoding up to 4 GB of the processor's memory address space. Host-initiated I/O cycles are decoded to PCI Express, DMI, or the MCH configuration space. Host-initiated memory cycles are decoded to PCI Express, DMI, or system memory. PCI Express device accesses to non-cacheable system memory are not snooped on the host bus. Memory accesses initiated from PCI Express using PCI semantics and from DMI to system memory will be snooped on the host bus.
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1.3.2
System Memory Interface
The MCH integrates a system memory DDR2 controller with two, 64-bit wide interfaces. Only Double Data Rate (DDR2) memory is supported; consequently, the buffers support only SSTL_1.8 V signal interfaces. The memory controller interface is fully configurable through a set of control registers. Features of the MCH memory controller include: * The MCH System Memory Controller directly supports one or two channels of memory (each channel consisting of 64 data lines). * Supports two memory addressing organization options: The memory channels are asymmetric: "Stacked" channels are assigned addresses serially. Channel B addresses are assigned after all Channel A addresses. The memory channels are interleaved: Addresses are ping-ponged between the channels after each cache line (64-B boundary). * Available bandwidth up to: 3.2 GB/s (DDR2 400) for single-channel mode 6.4 GB/s in dual-channel interleaved mode assuming DDR2 400 MHz. 8.5 GB/s in dual-channel interleaved mode assuming DDR2 533 MHz. * Supports DDR2 memory DIMM frequencies of 400 MHz and 533 MHz. The speed used in all channels is the speed of the slowest DIMM in the system. * I/O Voltage of 1.8 V for DDR2. * Supports non-ECC and ECC memory. * Supports 256-Mb, 512-Mb and 1-Gb DDR2 technologies * Supports only x8, x16, DDR2 devices with four banks and also supports eight bank, 1-Gbit DDR2 devices. * Supports opportunistic refresh * In dual channel mode the MCH supports 64 simultaneously open pages (four ranks of eight bank devices* 2 channels) * Supports Partial Writes to memory using Data Mask (DM) signals. * Supports page sizes of 4 KB, 8 KB, and 16 KB. * Supports a burst length of 8 for single-channel and dual-channel interleaved and asymmetric operating modes. * Supports unbuffered DIMMs. * SPD (Serial Presence Detect) scheme for DIMM detection support * Suspend-to-RAM support using CKE * Supports configurations defined in the JEDEC DDR2 DIMM specification only The MCH supports a memory thermal management scheme to selectively manage reads and/or writes. Memory thermal management can be triggered either by on-die thermal sensor, or by preset limits. Management limits are determined by weighted sum of various commands that are scheduled on the memory interface.
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1.3.3
Direct Media Interface (DMI)
Direct Media Interface (DMI) is the chip-to-chip connection between the MCH and ICH6. This high-speed interface integrates advanced priority-based servicing allowing for concurrent traffic and true isochronous transfer capabilities. Base functionality is completely software transparent permitting current and legacy software to operate normally. To provide for true isochronous transfers and configurable Quality of Service (QoS) transactions, the ICH6 supports two virtual channels on DMI: VC0 and VC1. These two channels provide a fixed arbitration scheme where VC1 is always the highest priority. VC0 is the default conduit of traffic for DMI and is always enabled. VC1 must be specifically enabled and configured at both ends of the DMI link (i.e., the ICH6 and MCH). Features of the DMI include: * A chip-to-chip connection interface to ICH6 * 2 GB/s point-to-point DMI to ICH6 (1 GB/s each direction) * 100 MHz reference clock (shared with PCI Express Graphics Attach). * 32-bit downstream addressing * APIC and MSI interrupt messaging support. Will send Intel-defined "End Of Interrupt" broadcast message when initiated by the processor. * Message Signaled Interrupt (MSI) messages * SMI, SCI and SERR error indication * Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port DMA, floppy drive, and LPC bus masters
1.3.4
PCI Express* Graphics Interface
The MCH contains a 16-lane (x16) PCI Express* port intended for an external PCI Express graphics card. The PCI Express port is compatible with the PCI Express Base Specification Revision 1.0a. The x16 port operates at a frequency of 2.5 Gb/s on each lane while employing 8b/10b encoding, and supports a maximum theoretical bandwidth of 4 Gb/s each direction.
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Features of the PCI Express Interface include: * One x16 PCI Express port intended for graphics attach, compatible with the PCI Express Base Specification revision 1.0a. * Theoretical PCI Express transfer rate of 2.5 Gb/s. * Raw bit-rate on the data pins of 2.5 Gb/s, resulting in a real bandwidth per pair of 250 MB/s given the 8b/10b encoding used to transmit data across this interface * Maximum theoretical realized bandwidth on the interface of 4 GB/s in each direction simultaneously, for an aggregate of 8 GB/s when (1)x16. * PCI Express Graphics Extended Configuration Space. The first 256 bytes of configuration space alias directly to the PCI Compatibility configuration space. The remaining portion of the fixed 4-KB block of memory-mapped space above that (starting at 100h) is known as extended configuration space. * PCI Express Enhanced Addressing Mechanism. Accessing the device configuration space in a flat memory mapped fashion. * Automatic discovery, negotiation, and training of link out of reset * Supports traditional PCI style traffic (asynchronous snooped, PCI ordering) * Supports traditional AGP style traffic (asynchronous non-snooped, PCI Express-relaxed ordering) * Hierarchical PCI-compliant configuration mechanism for downstream devices (i.e., normal PCI 2.3 Configuration space as a PCI-to-PCI bridge) * Supports "static" lane numbering reversal. This method of lane reversal is controlled by a Hardware Reset strap, and reverses both the receivers and transmitters for all lanes (e.g., TX15->TX0, RX15->RX0). This method is transparent to all external devices and is different than lane reversal as defined in the PCI Express Specification. In particular, link initialization is not affected by static lane reversal.
1.3.5
System Interrupts
The MCH interrupt support includes: * Supports both 8259 and Pentium 4 processor FSB interrupt delivery mechanisms. * Supports interrupts signaled as upstream Memory Writes from PCI Express and DMI MSIs routed directly to FSB From I/OxAPICs
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1.3.6
MCH Clocking
The differential FSB clock (HCLKP/HCLKN) is set to 200 MHz. This supports FSB transfer rates of 800 MT/s. The Host PLL generates 2X, 4X, and 8X versions of the host clock for internal optimizations. The MCH core clock is synchronized to the host clock. The internal and external memory clocks of 133 MHz and 200 MHz are generated from one of two MCH PLLs that use the host clock as a reference. This includes 2X and 4X for internal optimizations. The PCI Express core clock of 250 MHz is generated from a separate PCI Express PLL. This clock uses the fixed 100 MHz Serial Reference Clock (GCLKP/GCLKN) for reference. All of the above mentioned clocks are capable of tolerating Spread Spectrum clocking as defined in the Clock Generator specification. Host, Memory, and PCI Express* x16 Graphics PLLs, and all associated internal clocks are disabled until PWROK is asserted.
1.3.7
Power Management
MCH Power Management support includes: * PC99 suspend to DRAM support ("STR", mapped to ACPI state S3) * SMRAM space remapping to A0000h (128 KB) * Supports extended SMRAM space above 256 MB, additional 1-MB TSEG from the Base of graphics stolen memory (BSM) when enabled, and cacheable (cacheability controlled by processor) * ACPI Rev 1.0 compatible power management * Supports processor states: C0, C1, C2, C3, and C4 * Supports System states: S0, S1, S3, S4, and S5 * Supports processor Thermal Management 2 (TM2) * Microsoft Windows NT* Hardware Design Guide v1.0 compliant
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2
Signal Description
This chapter provides a detailed description of MCH signals. The signals are arranged in functional groups according to their associated interface. The states of all of the signals during reset are provided in the Section 2.9. The following notations are used to describe the signal type: I O I/O GTL+ Input pin Output pin Bi-directional input/output pin Open Drain GTL+ interface signal. Refer to the GTL+ I/O Specification for complete details. The MCH integrates GTL+ termination resistors, and supports VTT of from 0.83 V to 1.65 V (including guardbanding). PCI-Express interface signals. These signals are compatible with PCI Express 1.0 Signaling Environment AC Specifications and are AC coupled. The buffers are not 3.3 V tolerant. Differential voltage specification = (|D+ - D-|) * 2 = 1.2 V maximum Single-ended maximum = 1.5 V. Single-ended minimum = 0 V. Direct Media Interface signals. These signals are compatible with PCI Express 1.0 Signaling Environment AC Specifications, but are DC coupled. The buffers are not 3.3 V tolerant. Differential voltage specification = (|D+ - D-|) * 2 = 1.2 V maximum. Single-ended maximum = 1.5 V. Single-ended minimum = 0 V. CMOS buffers. 1.5 V tolerant. CMOS Open Drain buffers. 2.5 V tolerant. High Voltage CMOS buffers. 2.5 V tolerant. High Voltage CMOS input-only buffers. 3.3 V tolerant. Stub Series Termination Logic. These are 1.8 V output capable buffers. 1.8 V tolerant. Analog reference or output. May be used as a threshold voltage or for buffer compensation.
PCIE
DMI
CMOS COD HVCMOS HVIN SSTL-1.8 A
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Figure 2-1. Intel MCH Signal Interface Diagram
HA[31:3]# HD[63:0] HADS# HBNR# HBPRI# HDBSY# HDEFER# HDRDY# HEDRDY# HHIT# HHITM# HLOCK# HREQ[4:0]# HPCREQ# HTRDY# HRS[2:0]# HCPURST# HBREQ0# HDINV[3:0]# HADSTB[1:0]# HDSTBP[3:0]#, HDSTBN[3:0]# BSEL[2:0] HRCOMP HSCOMP HSWING HVREF SCS_A[3:0]# SMA_A[13:0] SBS_A[2:0] SRAS_A# SCAS_A# SWE_A# SDQ_A[63:0] SDM_A[7:0] SCB_A[7:0] SDQS_A[8:0], SDQS_A[8:0]# SCKE_A[3:0] SCLK_A[5:0], SCLK_A[5:0]# SODT_A[3:0] SCS_B[3:0]# SMA_B[13:0] SBS_B_B[2:0] SRAS_B# SCAS_B# SWE_B# SDQ_B[63:0] SDM_B[7:0] SCB_B[7:0] SDQS_B[8:0], SDQS_B[8:0]# SCKE_B[3:0] SCLK_B[5:0], SCLK_B[5:0]# SODT_B[3:0]
(R)
PCI Express x16 Graphics Port
EXP_RXN[15:0], EXP_RXP[15:0] EXP_TXN[15:0], EXP_TXP[15:0] EXP_COMPO EXP_COMPI EXP_SLR HCLKP, HCLKN GCLKP, GCLKN DREFCLKN, DREFCLKP RSTIN# PW ROK EXTTS# BSEL[2:0] MTYPE ICH_SYNC#
Processor System Bus Interface
Clocks, Reset, and Misc.
Direct Media Interface
DMI_RXP[3:0], DMI_RXN[3:0] DMI_TXP[3:0], DMI_TXN[3:0]
Voltage Reference, and Power System Memory DDR2 Channel A
VCC VTT VCC_EXP VCCSM VCC2 VCCA_EXPPLL VCCA_HPLL VCCA_SMPLL VSS
System Memory DDR2 Ref./ Comp.
SRCOMP[1:0] SOCOMP[1:0] SM_SLEWIN[1:0] SM_SLEWOUT[1:0] SMVREF[1:0]
System Memory DDR2 Channel B
Signal_Info
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2.1
Host Interface Signals
Note: Unless otherwise noted, the voltage level for all signals in this interface is tied to the termination voltage of the Host Bus (VTT).
Signal Name HADS# Type I/O GTL+ HBNR# I/O GTL+ HBPRI# O GTL+ Description Address Strobe: The processor bus owner asserts HADS# to indicate the first of two cycles of a request phase. The MCH can assert this signal for snoop cycles and interrupt messages. Block Next Request: This signal is used to block the current request bus owner from issuing new requests. This signal is used to dynamically control the processor bus pipeline depth. Priority Agent Bus Request: The MCH is the only Priority Agent on the processor bus. It asserts this signal to obtain the ownership of the address bus. This signal has priority over symmetric bus requests and will cause the current symmetric owner to stop issuing new transactions unless the HLOCK# signal was asserted. Bus Request 0: The MCH pulls the processor's bus HBREQ0# signal low during HCPURST#. The processor samples this signal on the active-toinactive transition of HCPURST#. The minimum setup time for this signal is 4 HCLKs. The minimum hold time is 2 clocks and the maximum hold time is 20 HCLKs. HBREQ0# should be tri-stated after the hold time requirement has been satisfied. CPU Reset: The HCPURST# pin is an output from the MCH. The MCH asserts HCPURST# while RSTIN# is asserted and for approximately 1 ms after RSTIN# is de-asserted. The HCPURST# allows the processors to begin execution in a known state. Note that the Intel(R) ICH6 must provide processor frequency select strap set-up and hold times around HCPURST#. This requires strict synchronization between MCH HCPURST# de-assertion and the Intel(R) ICH6 driving the straps. HDBSY# I/O GTL+ HDEFER# O GTL+ HDINV[3:0]# I/O GTL+ Data Bus Busy: This signal is used by the data bus owner to hold the data bus for transfers requiring more than one cycle. Defer: Signals that the MCH will terminate the transaction currently being snooped with either a deferred response or with a retry response. Dynamic Bus Inversion: Driven along with the HD[63:0] signals. Indicates if the associated signals are inverted or not. HDINV[3:0]# are asserted such that the number of data bits driven electrically low (low voltage) within the corresponding 16 bit group never exceeds 8. HDINVx# HDINV3# HDINV2# HDINV1# HDINV0# Data Bits HD[63:48] HD[47:32] HD[31:16] HD[15:0]
HBREQ0#
I/O GTL+
HCPURST#
O GTL+
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Signal Name HDRDY#
Type I/O GTL+
Description Data Ready: This signal is asserted for each cycle that data is transferred.
HEDRDY#
O GTL+
Early Data Ready: This signal indicates that the data phase of a read transaction will start on the bus exactly one common clock after assertion. Host Address Bus: HA[31:3]# connect to the processor address bus. During processor cycles, the HA[31:3]# are inputs. The MCH drives HA[31:3]# during snoop cycles on behalf of DMI and PCI Express Graphics initiators. HA[31:3]# are transferred at 2x rate. Host Address Strobe: The source synchronous strobes used to transfer HA[31:3]# and HREQ[4:0] at the 2x transfer rate. Host Data: These signals are connected to the processor data bus. Data on HD[63:0] is transferred at 4x rate. Note that the data signals may be inverted on the processor bus, depending on the HDINV[3:0]# signals. Differential Host Data Strobes: The differential source synchronous strobes are used to transfer HD[63:0]# and HDINV[3:0]# at 4x transfer rate. These signals are named this way because they are not level sensitive. Data is captured on the falling edge of both strobes. Hence, they are pseudo-differential, and not true differential. Strobes HDSTBP3#, HDSTBN3# HDSTBP2#, HDSTBN2# HDSTBP1#, HDSTBN1# HDSTBP0#, HDSTBN0# Data HD[63:48] HD[47:32] HD[31:16] HD[15:0] Bits HDINV3# HDINV2# HDINV1# HDINV0#
HA[31:3]#
I/O GTL+
HADSTB[1:0]#
I/O GTL+
HD[63:0]
I/O GTL+
HDSTBP[3:0]# HDSTBN[3:0]#
I/O GTL+
HHIT#
I/O GTL+
Hit: This signal indicates that a caching agent holds an unmodified version of the requested line. Also, driven in conjunction with HHITM# by the target to extend the snoop window. Hit Modified: This signal indicates that a caching agent holds a modified version of the requested line and that this agent assumes responsibility for providing the line. This signal is also driven in conjunction with HHIT# to extend the snoop window. Host Lock: All processor bus cycles sampled with the assertion of HLOCK# and HADS#, until the negation of HLOCK# must be atomic (i.e., no DMI or PCI Express Graphics accesses to DRAM are allowed when HLOCK# is asserted by the processor). Precharge Request: The processor provides a "hint" to the MCH that it is OK to close the DRAM page of the memory read request with which the hint is associated. The MCH uses this information to schedule the read request to memory using the special "AutoPrecharge" attribute. This causes the DRAM to immediately close (Precharge) the page after the read data has been returned. This allows subsequent processor requests to more quickly access information on other DRAM pages, since it will no longer be necessary to close an open page prior to opening the proper page. Asserted by the requesting agent during both halves of Request Phase. The same information is provided in both halves of the request phase.
HHITM#
I/O GTL+
HLOCK#
I/O GTL+
HPCREQ#
I GTL+ 2x
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Signal Name HREQ[4:0]#
Type I/O GTL+ 2x
Description Host Request Command: These signals define the attributes of the request. HREQ[4:0]# are transferred at 2x rate. They are asserted by the requesting agent during both halves of Request Phase. In the first half the signals define the transaction type to a level of detail that is sufficient to begin a snoop request. In the second half the signals carry additional information to define the complete transaction type. The transactions supported by the MCH Host Bridge are defined in the Host Interface section of this document.
HTRDY#
O GTL+
Host Target Ready: This signal indicates that the target of the processor transaction is able to enter the data transfer phase. Response Signals: These signals indicate the type of response as shown below: 000 = Response type 001 = Idle state 010 = Retry response 011 = Deferred response 100 = Reserved (not driven by MCH) 101 = Hard Failure (not driven by MCH) 110 = No data response 111 = Implicit Writeback 111 = Normal data response
HRS[2:0]#
O GTL+
BSEL[2:0]
I CMOS
Bus Speed Select: At the de-assertion of RSTIN#, the value sampled on these pins determines the expected frequency of the bus. Host RCOMP: Used to calibrate the Host GTL+ I/O buffers. This signal is powered by the Host Interface termination rail (VTT). Slew Rate Compensation: Compensation for the Host Interface.
HRCOMP
I/O CMOS
HSCOMP
I/O CMOS
HSWING
I A
Host Voltage Swing: This signal provides the reference voltage used by FSB RCOMP circuits. HSWING is used for the signals handled by HRCOMP. Host Reference Voltage Reference: Voltage input for the data, address, and common clock signals of the Host GTL interface.
HVREF
I A
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2.2
DDR2 DRAM Channel A Interface
Signal Name SCLK_A[5:0] Type O SSTL-1.8 Description SDRAM Differential Clock: (3 per DIMM). SCLK_Ax and its complement SCLK_Ax# signal make a differential clock pair output. The crossing of the positive edge of SCLK_Ax and the negative edge of its complement SCLK_Ax# are used to sample the command and control signals on the SDRAM. SDRAM Complementary Differential Clock: (3 per DIMM) These are the complementary differential DDR2 Clock signals. Chip Select: (1 per Rank) These signals select particular SDRAM components during the active state. There is one chip select for each SDRAM rank. Memory Address: These signals are used to provide the multiplexed row and column address to the SDRAM Bank Select: These signals define which banks are selected within each SDRAM rank DDR2: 1-Gb technology is 8 banks. SRAS_A# SCAS_A# SWE_A# SDQ_A[63:0] O SSTL-1.8 O SSTL-1.8 O SSTL-1.8 I/O SSTL-1.8 2x O SSTL-1.8 2X I/O SSTL-1.8 2X I/O SSTL-1.8 2x I/O SSTL-1.8 2x O SSTL-1.8 O SSTL-1.8 Row Address Strobe: This signal is used with SCAS_A# and SWE_A# (along with SCS_A#) to define the SDRAM commands. Column Address Strobe: This signal is used with SRAS_A# and SWE_A# (along with SCS_A#) to define the SDRAM commands. Write Enable: This signal is used with SCAS_A# and SRAS_A# (along with SCS_A#) to define the SDRAM commands. Data Lines: SDQ_A signals interface to the SDRAM data bus.
SCLK_A[5:0]# SCS_A[3:0]#
O SSTL-1.8 O SSTL-1.8 O SSTL-1.8 O SSTL-1.8
SMA_A[13:0] SBS_A[2:0]
SDM_A[7:0]
Data Mask: When activated during writes, the corresponding data groups in the SDRAM are masked. There is one SDM_Ax signal for every data byte lane. ECC Check Byte: These signals require a 6-layer board to be routed.
SCB_A[7:0]
SDQS_A[8:0]
Data Strobes: For DDR2, SDQS_Ax and its complement SDQS_Ax# signal make up a differential strobe pair. The data is captured at the crossing point of SDQS_Ax and its complement SDQS_Ax# during read and write transactions. Data Strobe Complements: These signals are the complementary DDR2 strobe signals. Clock Enable: (1 per Rank) SACKE is used to initialize the SDRAMs during power-up, to power-down SDRAM ranks, and to place all SDRAM ranks into and out of self-refresh during Suspend-to-RAM. On Die Termination: Active On-die Termination Control signals for DDR2 devices.
SDQS_A[8:0]#
SCKE_A[3:0]
SODT_A[3:0]
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2.3
DDR2 DRAM Channel B Interface
Signal Name SCLK_B[5:0] Type O SSTL-1.8 Description SDRAM Differential Clock: (3 per DIMM) SCLK_Bx and its complement SCLK_Bx# signal make a differential clock pair output. The crossing of the positive edge of SCLK_Bx and the negative edge of its complement SCLK_Bx# are used to sample the command and control signals on the SDRAM. SDRAM Complementary Differential Clock: (3 per DIMM) These are the complementary differential DDR2 clock signals. Chip Select: (1 per Rank) These signals select particular SDRAM components during the active state. There is one chip select for each SDRAM rank Memory Address: These signals are used to provide the multiplexed row and column address to the SDRAM Bank Select: These signals define which banks are selected within each SDRAM rank DDR2: 1-Gb technology is 8 banks. SRAS_B# SCAS_B# SWE_B# SDQ_B[63:0] O SSTL-1.8 O SSTL-1.8 O SSTL-1.8 I/O SSTL-1.8 2x O SSTL-1.8 2x I/O SSTL-1.8 2X I/O SSTL-1.8 2x I/O SSTL-1.8 2x O SSTL-1.8 O SSTL-1.8 Row Address Strobe: This signal is used with SCAS_B# and SWE_B# (along with SCS_B#) to define the SDRAM commands Column Address Strobe: This signal is used with SRAS_B# and SWE_B# (along with SCS_B#) to define the SDRAM commands. Write Enable: This signal is used with SCAS_B# and SRAS_B# (along with SCS_B#) to define the SDRAM commands. Data Lines: SDQ_Bx signals interface to the SDRAM data bus
SCLK_B[5:0]# SCS_B[3:0]#
O SSTL-1.8 O SSTL-1.8 O SSTL-1.8 O SSTL-1.8
SMA_B[13:0] SBS_B[2:0]
SDM_B[7:0]
Data Mask: When activated during writes, the corresponding data groups in the SDRAM are masked. There is one SDM_Bx signal for every data byte lane. ECC Check Byte: These signals require a 6-layer board to be routed.
SCB_B[7:0]
SDQS_B[8:0]
Data Strobes: For DDR2, SDQS_Bx and its complement SDQS_Bx# make up a differential strobe pair. The data is captured at the crossing point of SDQS_Bx and its complement SDQS_Bx# during read and write transactions. Data Strobe Complements: These signals are the complementary DDR2 strobe signals. Clock Enable: (1 per Rank) SCKE_B is used to initialize the SDRAMs during power-up, to power-down SDRAM ranks, and to place all SDRAM ranks into and out of self-refresh during Suspend-to-RAM. On Die Termination: Active On-die Termination Control signals for DDR2 devices.
SDQS_B[8:0]#
SCKE_B[3:0]
SODT_B[3:0]
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2.4
DDR2 DRAM Reference and Compensation
Signal Name SRCOMP[1:0] SOCOMP[1:0] SM_SLEWIN[1:0] Type I/O I/O A I A SM_SLEWOUT[1:0] O A SMVREF[1:0] I A System Memory RCOMP DDR2 On-Die DRAM Over Current Detection (OCD) driver compensation Buffer Slew Rate Input: Slew Rate Characterization buffer input for X and Y orientation. Buffer Slew Rate Output: Slew Rate Characterization buffer output for X and Y orientation SDRAM Reference Voltage: Reference voltage inputs for each DQ, DM, DQS, and DQS# input signals. Description
2.5
PCI Express* x16 Graphics Port Signals
Unless otherwise specified, PCI Express Graphics signals are AC coupled, so the only voltage specified is a maximum 1.2 V differential swing.
Signal Name EXP_RXN[15:0] EXP_RXP[15:0] EXP_TXN[15:0] EXP_TXP[15:0] EXP_COMPO Type I/O PCIE O PCIE I A EXP_COMPI I A EXP_SLR I CMOS PCI Express Graphics Output Current Compensation Note: EXP_COMP0 is used for DMI current compensation. PCI Express Graphics Input Current Compensation Note: EXP_COMPI is used for DMI current compensation. PCI Express* Static Lane Reversal: The MCH's PCI Express lane numbers are reversed. For example, the MCH PCI Express interface signals can be configured as follows: Ball C10 A9 ... N3 P1 Normal Operation EXP_TXP0 EXP_TXP1 ... EXP_TXP14... EXP_TXP15 Lane Reversed EXP_TXP15 EXP_TXP14 ... EXP_TXP1... EXP_TXP0 PCI Express Graphics Transmit Differential Pair Description PCI Express Graphics Receive Differential Pair
0 = MCH's PCI Express lane numbers are reversed 1 = Normal operation
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2.6
Clocks, Reset, and Miscellaneous
Signal Name HCLKP HCLKN GCLKP GCLKN Type I CMOS I CMOS Description Differential Host Clock In: These pins receive a differential host clock from the external clock synthesizer. This clock is used by all of the MCH logic that is in the Host clock domain. Differential PCI Express Graphics Clock In: These pins receive a differential 100 MHz serial reference clock from the external clock synthesizer. This clock is used to generate the clocks necessary for the support of PCI Express. Display PLL Differential Clock In
DREFCLKN DREFCLKP RSTIN#
I CMOS I HVIN
Reset In: When asserted, this signal will asynchronously reset the MCH logic. This signal is connected to the PLTRST# output of the Intel(R) ICH6. All PCI Express Graphics Attach output signals will also tri-state compatible with PCI Express* Specification Rev 1.0a. This input should have a Schmitt trigger to avoid spurious resets. This signal is required to be 3.3 V tolerant.
PWROK
I HVIN
Power OK: When asserted, PWROK is an indication to the MCH that core power has been stable for at least 10 us. External Thermal Sensor Input: This signal may connect to a precision thermal sensor located on or near the DIMMs. If the system temperature reaches a dangerously high value, then this signal can be used to trigger the start of system thermal management. This signal is activated when an increase in temperature causes a voltage to cross some threshold in the sensor. Memory Type Select Strap. This signal is a strapping option that indicates the type of system memory. This signal should be tied to ground indicating DDR2 memory. ICH Sync: This signal is connected to the MCH_SYNCH# signal on the ICH6.
EXTTS#
I HVCMOS
MTYPE
I CMOS
ICH_SYNC#
O HVCMOS
2.7
Direct Media Interface (DMI)
Signal Name DMI_RXP[3:0] DMI_RXN[3:0] DMI_TXP[3:0] DMI_TXN[3:0] Type I/O DMI O DMI Description Direct Media Interface: These signals are the receive differential pair (Rx). Direct Media Interface: These signals are the transmit differential pair (Tx).
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2.8
Power and Ground
Name VCC VTT VCC_EXP VCCSM Voltage 1.5 V 1.2 V 1.5 V 1.8 V Core Power. Processor System Bus Power. PCI Express* and DMI Power. System Memory Power. DDR2: VCCSM = 1.8 V VCC2 VCCA_EXPPLL VCCA_HPLL VCCA_SMPLL VSS 2.5 V 1.5 V 1.5 V 1.5 V 0V 2.5 V CMOS Power. PCI Express PLL Analog Power. Host PLL Analog Power. System Memory PLL Analog Power. Ground. Description
2.9
Reset States and Pull-up/Pull-downs
This section describes the expected states of the MCH I/O buffers during and immediately after the assertion of RSTIN#. This table only refers to the contributions on the interface from the MCH and does not reflect any external influence (such as external pull-up/pull-down resistors or external drivers).
Legend:
CMCT: DRIVE: TERM: LV: HV: IN: ISO: TRI: PU: PD: STRAP: Common Mode Center Tapped. Differential signals are weakly driven to the common mode central voltage. Strong drive (to normal value supplied by core logic if not otherwise stated) Normal termination devices are turned on Low voltage High voltage Input buffer enabled Isolate input buffer so that it does not oscillate if input left floating Tri-state Weak internal pull-up Weak internal pull-down Strap input sampled during assertion or on the de-asserting edge of RSTIN#
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Table 2-1. Host Interface Reset and S3 States
Interface Host I/F Signal Name HCPURST# HADSTB[1:0]# HA[31:3]# HD[63:0] HDSTBP[3:0]# HDSTBN[3:0]# HDINV[3:0]# HADS# HBNR# HBPRI# HDBSY# HDEFER# HDRDY# HEDRDY# Host I/F HHIT# HHITM# HLOCK# HREQ[4:0]# HTRDY# HRS[2:0]# HBREQ0# HPCREQ# HVREF HRCOMP I/O O I/O I/O I/O I/O I/O I/O I/O I/O O I/O O I/O O I/O I/O I/O I/O O O I/O I I I/O State During RSTIN# Assertion DRIVE LV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV IN TRI State After RSTIN# Deassertion TERM HV after approximately 1ms TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV IN TRI after RCOMP S3 Pull-up/ Pull-down
TRI (No VTT) TRI (No VTT) TRI (No VTT) TRI (No VTT) TRI (No VTT) TRI (No VTT) TRI (No VTT) TRI (No VTT) TRI (No VTT) TRI (No VTT) TRI (No VTT) TRI (No VTT) TRI (No VTT) TRI (No VTT) TRI (No VTT) TRI (No VTT) TRI (No VTT) TRI (No VTT) TRI (No VTT) TRI (No VTT) TRI (No VTT) TRI (No VTT) TRI TRI 20 resistor for board with target impedance of 60
HSWING HSCOMP
I I/O
IN TRI
IN TRI TRI
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Table 2-2. System Memory Reset and S3 States
Interface System Memory Signal Name Channel A SCLK_A[5:0] SCLK_A[5:0]# SCS_A[3:0]# SMA_A[13:0] SBS_A[2:0] SRAS_A# SCAS_A# SWE_A# SDQ_A[63:0] SDM_A[7:0] SCB_A[7:0] SDQS_A[8:0] SDQS_A[8:0]# SCKE_A[3:0] SODT_A[3:0] System Memory Channel B SCLK_B[5:0] SCLK_B[5:0]# SCS_B[3:0]# SMA_B[13] SMA_B[12:11] SMA_B[10:8] SMA_B[7] SMA_B[6:0] SBS_B[2] SBS_B[1:0] SRAS_B# SCAS_B# SWE_B# SDQ_B[63:0] SDM_B[7:0] SCB_B[7:0] SDQS_B[8:0] O O O O O O O O O O O O O I/O O I/O I/O TRI TRI TRI TRI LV TRI LV TRI LV TRI TRI TRI TRI TRI TRI TRI TRI TRI TRI TRI TRI LV TRI LV TRI LV TRI TRI TRI TRI TRI TRI TRI TRI TRI TRI TRI TRI LV TRI LV TRI LV TRI TRI TRI TRI TRI TRI TRI TRI O O O O O O O O I/O O I/O I/O I/O O O TRI TRI TRI TRI TRI TRI TRI TRI TRI TRI TRI TRI TRI LV LV TRI TRI TRI TRI TRI TRI TRI TRI TRI TRI TRI TRI TRI LV LV TRI TRI TRI TRI TRI TRI TRI TRI TRI TRI TRI TRI TRI LV LV I/O State During RSTIN# Assertion State After RSTIN# Deassertion S3 Pull-up/ Pull-down
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Signal Description
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Interface
Signal Name SDQS_B[8:0]# SCKE_B[3:0] SODT_B[3:0] SRCOMP0 SRCOMP1 SM_SLEWIN[1:0] SM_SLEWOU[1:0] SMVREF[1:0] SOCOMP[1:0]
I/O I/O O O I/O I/O I O I I/O
State During RSTIN# Assertion TRI LV LV TRI TRI IN TRI IN TRI
State After RSTIN# Deassertion TRI LV LV TRI (after RCOMP) TRI (after RCOMP) IN TRI (after RCOMP) IN TRI
S3
Pull-up/ Pull-down
TRI LV LV TRI TRI IN TRI IN TRI DDR2: 40 resistor to ground
Table 2-3. PCI Express* Graphics x16 Port Reset and S3 States
Interface PCI Express*Graphics Signal Name EXP_RXN[15:0] EXP_RXP[15:0] EXP_TXN[15:0] EXP_TXP[15:0] EXP_COMPO EXP_COMPI I/O I/O I/O O O I I State During RSTIN# Assertion CMCT CMCT CMCT 1.0 V CMCT 1.0 V TRI TRI State After RSTIN# De-assertion CMCT CMCT CMCT 1.0 V CMCT 1.0 V TRI (after RCOMP) TRI (after RCOMP) S3 Pull-up/ Pull-down
CMCT CMCT CMCT 1.0 V CMCT 1.0 V TRI TRI
Table 2-4. DMI Reset and S3 States
Interface DMI Signal Name DMI_RXN[3:0] DMI_RXP[3:0] DMI_TXN[3:0] DMI_TXP[3:0] I/O I/O I/O O O State During RSTIN# Assertion CMCT CMCT CMCT 1.0 V CMCT 1.0 V State After RSTIN# De-assertion CMCT CMCT CMCT 1.0 V CMCT 1.0 V S3 Pull-up/ Pulldown
CMCT CMCT CMCT 1.0 V CMCT 1.0 V
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Table 2-5. Clocking Reset and S3 States
Interface Clocks Signal Name HCLKN HCLKP GCLKN GCLKP DREFCLKN DREFCLKP I/O I I I I I I State During RSTIN# Assertion IN IN IN IN IN IN State After RSTIN# Deassertion IN IN IN IN IN IN S3 Pull-up/ Pull-down
IN IN IN IN IN IN
Table 2-6. Miscellaneous Reset and S3 States
Interface Misc. Signal Name RSTIN# PWROK EXTTS# BSEL[2:0] MTYPE EXP_SLR ICH_SYNC# I/O I I I I I I O State During RSTIN# Assertion IN HV PU TRI TERM HV TERM HV PU State After RSTIN# De-assertion IN HV PU TRI TERM HV TERM HV PU S3 Pull-up/ Pull-down
IN HV PU TRI TERM HV TERM HV PU
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Register Description
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3
Register Description
The MCH contains two sets of software accessible registers, accessed via the processor I/O address space: Control registers and internal configuration registers. * Control registers are I/O mapped into the processor I/O space that control access to PCI and PCI Express configuration space (see Section 3.4). * Internal configuration registers residing within the MCH are partitioned into two logical device register sets ("logical" since they reside within a single physical device). The first register set is dedicated to Host Bridge functionality (i.e. DRAM configuration, other chip-set operating parameters and optional features). The second register block is dedicated to HostPCI Express Bridge functions (controls PCI Express interface configurations and operating parameters). The MCH internal registers (I/O Mapped, Configuration and PCI Express Extended Configuration registers) are accessible by the processor. The registers that reside within the lower 256 bytes of each device can be accessed as Byte, Word (16-bit), or DWord (32-bit) quantities, with the exception of CONFIG_ADDRESS that can only be accessed as a DWord. All multi-byte numeric fields use "little-endian" ordering (i.e., lower addresses contain the least significant parts of the field). Registers that reside in bytes 256 through 4095 of each device may only be accessed using memory mapped transactions in DWord (32-bit) quantities.
3.1
Register Terminology
The following table shows the register-related terminology that is used.
Item RO RS/WC Description Read Only bit(s). Writes to these bits have no effect. Read Set / Write Clear bit(s). These bits are set to `1' when read and then will continue to remain set until written. A write of `1' clears (sets to `0') the corresponding bit(s) and a write of `0' has no effect. Read / Write bit(s). These bits can be read and written. Read / Write Clear bit(s). These bits can be read. Internal events may set this bit. A write of `1' clears (sets to `0') the corresponding bit(s) and a write of `0' has no effect. Read / Write Clear / Sticky bit(s). These bits can be read. Internal events may set this bit. A write of `1' clears (sets to `0') the corresponding bit(s) and a write of `0' has no effect. Bits are not cleared by "warm" reset, but will be reset with a cold/complete reset (for PCI Express* related bits a cold reset is "Power Good Reset" as defined in the PCI Express* Specification). Read / Write / Lockable bit(s). These bits can be read and written. Additionally there is a bit (which may or may not be a bit marked R/W/L) that, when set, prohibits this bit field from being writeable (bit field becomes Read Only). Read / Write / Sticky bit(s). These bits can be read and written. Bits are not cleared by "warm" reset, but will be reset with a cold/complete reset (for PCI Express related bits a cold reset is "Power Good Reset" as defined in the PCI Express* Specification).
R/W R/WC R/WC/S
R/W/L
R/W/S
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Item R/WSC
Description Read / Write Self Clear bit(s). These bits can be read and written. When the bit is `1', hardware may clear the bit to `0' based upon internal events, possibly sooner than any subsequent read could retrieve a `1'. Read / Write Self Clear / Lockable bit(s). These bits can be read and written. When the bit is `1', hardware may clear the bit to `0' based upon internal events, possibly sooner than any subsequent read could retrieve a `1'. Additionally there is a bit (which may or may not be a bit marked R/W/L) that, when set, prohibits this bit field from being writeable (bit field becomes Read Only). Read Write Clear bit(s). These bits can be read and written. However, a write of `1' clears (sets to `0') the corresponding bit(s) and a write of `0' has no effect. Write Once bit(s). Once written, bits with this attribute become Read Only. These bits can only be cleared by a Reset. Write Only. Whose bits may be written, but will always-return zeros when read. They are used for write side effects. Any data written to these registers cannot be retrieved. Some of the MCH registers described in this section contain reserved bits. These bits are labeled "Reserved". Software must deal correctly with fields that are reserved. On reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. On writes, software must ensure that the values of reserved bit positions are preserved. That is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back. Note the software does not need to perform read, merge, and write operation for the configuration address register. In addition to reserved bits within a register, the MCH contains address locations in the configuration space of the Host Bridge entity that are marked either "Reserved" or "Intel Reserved". The MCH responds to accesses to "Reserved" address locations by completing the host cycle. When a "Reserved" register location is read, a zero value is returned. ("Reserved" registers can be 8-, 16-, or 32-bits in size). Writes to "Reserved" registers have no effect on the MCH. Registers that are marked as "Intel Reserved" must not be modified by system software. Writes to "Intel Reserved" registers may cause system failure. Reads from "Intel Reserved" registers may return a non-zero value. Upon a Full Reset, the MCH sets its entire set of internal configuration registers to predetermined default states. Some register values at reset are determined by external strapping options. The default state represents the minimum functionality feature set required to successfully bringing up the system. Hence, it does not represent the optimal system configuration. It is the responsibility of the system initialization software (usually BIOS) to properly determine the DRAM configurations, operating parameters and optional system features that are applicable, and to program the MCH registers accordingly.
R/WSC/L
R/WC R/WO W Reserved Bits
Reserved Registers
Default Value
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3.2
Platform Configuration
In platforms that support DMI (e.g. this MCH) the configuration structure is significantly different from previous Hub architectures. The DMI physically connects the MCH and the Intel ICH6; so, from a configuration standpoint, the DMI is logically PCI bus 0. As a result, all devices internal to the MCH and the Intel ICH6 appear to be on PCI bus 0. The ICH6 internal LAN controller does not appear on bus 0; it appears on the external PCI bus (whose number is configurable). The system's primary PCI expansion bus is physically attached to the Intel ICH6 and, from a configuration perspective, appears to be a hierarchical PCI bus behind a PCI-to-PCI bridge and therefore has a programmable PCI Bus number. The PCI Express Graphics Attach appears to system software to be a real PCI bus behind a PCI-to-PCI bridge that is a device resident on PCI bus 0. Note: A physical PCI bus 0 does not exist and that DMI and the internal devices in the MCH and Intel ICH6 logically constitute PCI Bus 0 to configuration software. This is shown in Figure 3-1.
Figure 3-1. Conceptual Intel 925X Express Chipset Platform PCI Configuration Diagram
(R)
Processor
Intel(R) 82925X MCH PCI Configuration Window in I/O Space
DRAM Controller Interface Bus 0, Device 0 PCI Express* Bus 0, Device 1
DMI
Intel(R) ICH6 PCI Configuration Window in I/O Space
LPC Device Bus 0, Device 31 Function 0
DMI PCI Bridge (P2) Bus 0, Device 30 Function0
PCI_Config_Dia
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The MCH contains the following PCI devices within a single physical component. The configuration registers for the devices are mapped as devices residing on PCI bus 0. * Device 0 - Host Bridge/DRAM Controller: Logically this appears as a PCI device residing on PCI bus 0. Device 0 contains the standard PCI header registers, PCI Express base address register, DRAM control (including thermal/throttling control), and configuration for the DMI and other MCH specific registers. * Device 1- Host-PCI Express Bridge. Logically this appears as a "virtual" PCI-to-PCI bridge residing on PCI bus 0 and is compliant with PCI Express* Specification Revision 1.0a. Device 1 contains the standard PCI-to-PCI bridge registers and the standard PCI Express/PCI configuration registers (including the PCI Express memory address mapping). It also contains Isochronous and Virtual Channel controls in the PCI Express extended configuration space. Table 3-1. Device Number Assignment for Internal MCH Devices
MCH Function Host Bridge / DRAM Controller Host-to-PCI Express* Bridge (virtual P2P) Device# Device 0 Device 1
3.3
General Routing Configuration Accesses
The MCH supports two PCI related interfaces: DMI and PCI Express. PCI and PCI Express configuration cycles are selectively routed to one of these interfaces. The MCH is responsible for routing configuration cycles to the proper interface. Configuration cycles to the Intel ICH6 internal devices and Primary PCI (including downstream devices) are routed to the Intel ICH6 via DMI. Configuration cycles to both the PCI Express Graphics PCI compatibility configuration space and the PCI Express Graphics extended configuration space are routed to the PCI Express Graphics port. A detailed description of the mechanism for translating processor I/O bus cycles to configuration cycles is described below.
3.3.1
Standard PCI Bus Configuration Mechanism
The PCI Bus defines a slot based "configuration space" that allows each device to contain up to 8 functions with each function containing up to 256 8-bit configuration registers. The PCI specification defines two bus cycles to access the PCI configuration space: Configuration Read and Configuration Write. Memory and I/O spaces are supported directly by the processor. Configuration space is supported by a mapping mechanism implemented within the MCH. The configuration access mechanism makes use of the CONFIG_ADDRESS Register (at I/O address 0CF8h though 0CFBh) and CONFIG_DATA Register (at I/O address 0CFCh though 0CFFh). To reference a configuration register a DW I/O write cycle is used to place a value into CONFIG_ADDRESS that specifies the PCI bus, the device on that bus, the function within the device, and a specific configuration register of the device function being accessed. CONFIG_ADDRESS [31] must be 1 to enable a configuration cycle. CONFIG_DATA then becomes a window into the four bytes of configuration space specified by the contents of CONFIG_ADDRESS. Any read or write to CONFIG_DATA will result in the MCH translating the CONFIG_ADDRESS into the appropriate configuration cycle.
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Register Description
R
The MCH is responsible for translating and routing the processor's I/O accesses to the CONFIG_ADDRESS and CONFIG_DATA registers to internal MCH configuration registers, DMI, or PCI Express.
3.3.2
Logical PCI Bus 0 Configuration Mechanism
The MCH decodes the Bus Number (bits 23:16) and the Device Number fields of the CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0 the configuration cycle is targeting a PCI Bus 0 device. The Host-DMI Bridge entity within the MCH is hardwired as Device 0 on PCI Bus 0. The Host-PCI Express Bridge entity within the MCH is hardwired as Device 1 on PCI Bus 0. The Intel ICH6 decodes the Type 0 access and generates a configuration access to the selected internal device.
3.3.3
Primary PCI and Downstream Configuration Mechanism
If the Bus Number in the CONFIG_ADDRESS is non-zero, and falls outside the range claimed by the Host-PCI Express bridge (not between upper bound in device's Subordinate Bus Number register and lower bound in device's Secondary Bus Number register), the MCH would generate a Type 1 DMI configuration cycle. This DMI configuration cycle will be sent over the DMI. If the cycle is forwarded to the Intel ICH6 via the DMI, the Intel ICH6 compares the non-zero Bus Number with the Secondary Bus Number and Subordinate Bus Number registers of its P2P bridges to determine if the configuration cycle is meant for ICH6 PCI Express ports one of the Intel ICH6's devices, the DMI, or a downstream PCI bus.
Figure 3-2. DMI Type 0 Configuration Address Translation
Configuration Address 31 1 30 Reserved 24 23 Bus Number 16 15 Device Number 11 10 Function 87 Double Word 21 XX 0
DMI Type 0 Configuration Address Extension OCFBh 31 1 30 Reserved 24 23 Bus Number OCFAh 16 15 Device Number OCF9h 11 10 Function 87 Double Word OCF8h 21 00 0
DMI_Typ0_Config
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Figure 3-3. DMI Type 1 Configuration Address Translation
Configuration Address 31 1 30 Reserved 24 23 Bus Number 16 15 Device Number 11 10 Function 87 Double Word 21 XX 0
DMI Type 1 Configuration Address Extension OCFBh Reserved OCFAh OCF9h Device Number OCF8h Double Word
31 1
30
24 23
16 15
11 10 Function
87
21 00
0
Bus Number
DMI_Typ1_Config
3.3.4
PCI Express* Enhanced Configuration Mechanism
PCI Express extends the configuration space to 4096 bytes per device/function as compared to 256 bytes allowed by PCI Specification, Revision 2.3. PCI Express configuration space is divided into a PCI 2.3 compatible region that consists of the first 256B of a logical device's configuration space and a PCI Express extended region that consists of the remaining configuration space. The PCI compatible region can be accessed using either the mechanism defined in the previous section or using the enhanced PCI Express configuration access mechanism described in this section. The extended configuration registers may only be accessed using the enhanced PCI Express configuration access mechanism. To maintain compatibility with PCI configuration addressing mechanisms, system software must access the extended configuration space using 32bit operations (32-bit aligned) only. These 32-bit operations include byte enables allowing only appropriate bytes within the DWord to be accessed. Locked transactions to the PCI Express memory mapped configuration address space are not supported. All changes made using either access mechanism are equivalent. The enhanced PCI Express configuration access mechanism uses a flat memory-mapped address space to access device configuration registers. This address space is reported by the system firmware to the operating system. The PCIEXBAR register defines the base address for the 256-MB block of addresses below top of addressable memory (currently 4 GB) for the configuration space associated with all devices and functions that are potentially a part of the PCI Express root complex hierarchy. The PCI Express Configuration Transaction Header includes an additional 4 bits (Extended Register Address[3:0]) between the Function Number and Register Address fields to provide indexing into the 4 KB of configuration space allocated to each potential device. For PCI Compatible Configuration Requests, the Extended Register Address field must be all zeros.
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Register Description
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Figure 3-4. Memory Map to PCI Express* Device Configuration Space
0xFFFFFFFh Bus 255 0xFFFFFh Device 31 0xFFFFFh Function 7 PCI Express Extended Configuration Space 0xFFFh
0x1FFFFFh Bus 1 0xFFFFFh Bus 0 0h
0xFFFFh Device 1 0x7FFFh Device 0
0xFFFFh Function 1 0x7FFFh Function 0
0xFFh
PCI Compatible Config Space PCI Compatible Config Header
0x3Fh
Located By PCI Express Base Address
MemMap_PCIExpress
Just the same as with PCI devices, each device is selected based on decoded address information that is provided as a part of the address portion of Configuration Request packets. A PCI Express device will decode all address information fields (bus, device, function, and extended address numbers) to provide access to the correct register. To access this space (steps 1, 2, 3 are performed only once by BIOS) 1. Use the PCI compatible configuration mechanism to enable the PCI Express enhanced configuration mechanism by writing 1 to bit 31 of the DEVEN register. 2. Use the PCI compatible configuration mechanism to write an appropriate PCI Express base address into the PCIEXBAR register. 3. Calculate the host address of the register you wish to set using (PCI Express base + (bus number * 1 MB) + (device number * 32 KB) + (function number * 4 KB) + (1 B * offset within the function) = host address). 4. Use a memory write or memory read cycle to the calculated host address to write to or read from that register.
31 28 Base 27 Bus 20 19 Device 15 14 12 11 8 7 Register Number 2 1 X 0 X
Function Extended
Config_Write
PCI Express Configuration Writes
Internally the host interface unit translates writes to PCI Express extended configuration space to configurations on the backbone. Writes to extended space are posted on the FSB, but non-posted on the PCI Express* x16 Graphics Interface or DMI pins (i.e., translated to configuration writes). See the PCI Express Specification for more information on both the PCI 2.3 compatible and PCI Express enhanced configuration mechanism and transaction rules.
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3.3.5
Intel(R) 82925X MCH Configuration Cycle Flowchart
(R)
Figure 3-5. Intel 82925X MCH Configuration Cycle Flowchart
DW I/O Write to CONFIG_ADDRES S with bit 31 = 1
I/O Read/Write to CONFIG_DATA
Bus# = 0
Yes
No
MCH Generates Type 1 Access to PCI Express
Yes
Bus# > Sec Bus Bus# Sub Bus in MCH Dev 1
Device# = 0 Function# = 0
Yes
MCH Claims
No
No
Yes
Bus# = Secondary Bus in MCH Dev 1
Device# = 1 & Dev # 1 Enabled & Function# = 0
Yes
MCH Claims
No
No
MCH Generates MISI Type 1Configuration Cycle
Device# = 2 & Dev# 2 Enabled & Function# = 0 or 1
Yes
MCH Claims
No
Device# = 0
Yes
MCH Generates Type 0 Accessto PCI Express
GMCH Generates DMI Type 0 Configuration Cycle
No
MCH allows cycle to go to DMI resulting in Master Abort
Config_Cyc_Flow_915
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Register Description
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3.4
I/O Mapped Registers
The MCH contains two registers that reside in the processor I/O address space - the Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data (CONFIG_DATA) Register. The Configuration Address Register enables/disables the configuration space and determines what portion of configuration space is visible through the Configuration Data window.
3.4.1
CONFIG_ADDRESS--Configuration Address Register
I/O Address: Default Value: Access: Size: 0CF8h Accessed as a DWord 00000000h R/W 32 bits
CONFIG_ADDRESS is a 32-bit register that can be accessed only as a DW. A Byte or Word reference will "pass through" the Configuration Address Register and DMI onto the Primary PCI bus as an I/O cycle. The CONFIG_ADDRESS register contains the Bus Number, Device Number, Function Number, and Register Number for which a subsequent configuration access is intended.
Bit Access & Default R/W 0b Configuration Enable (CFGE): 1 = Enable 0 = Disable Reserved R/W 00h Bus Number: If the Bus Number is programmed to 00h the target of the Configuration Cycle is a PCI Bus #0 agent. If this is the case and the MCH is not the target (i.e., the device number is 3 and not equal to 7), then a DMI Type 0 Configuration Cycle is generated. If the Bus Number is non-zero, and does not fall within the ranges enumerated by device 1's Secondary Bus Number or Subordinate Bus Number Register, then a DMI Type 1 Configuration Cycle is generated. If the Bus Number is non-zero and matches the value programmed into the Secondary Bus Number Register of device 1, a Type 0 PCI configuration cycle will be generated on PCI Express Graphics. If the Bus Number is non-zero, greater than the value in the Secondary Bus Number register of device 1 and less than or equal to the value programmed into the Subordinate Bus Number Register of device 1 a Type 1 PCI configuration cycle will be generated on PCI Express Graphics. This field is mapped to byte 8 [7:0] of the request header format during PCI Express Configuration cycles and A[23:16] during the DMI Type 1 configuration cycles. 15:11 R/W 00h Device Number: This field selects one agent on the PCI bus selected by the Bus Number. When the Bus Number field is "00", the MCH decodes the Device Number field. The MCH is always Device Number 0 for the Host bridge entity, Device Number 1 for the Host-PCI Express entity. Therefore, when the Bus Number =0 and the Device Number equals 0, 1, or 2 the internal MCH devices are selected. This field is mapped to byte 6 [7:3] of the request header format during PCI Express Configuration cycles and A [15:11] during the DMI configuration cycles. Description
31
30:24 23:16
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Register Description
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Bit
Access & Default R/W 000b
Description
10:8
Function Number: This field allows the configuration registers of a particular function in a multi-function device to be accessed. The MCH ignores configuration cycles to its internal devices if the function number is not equal to 0 or 1. This field is mapped to byte 6 [2:0] of the request header format during PCI Express Configuration cycles and A[10:8] during the DMI configuration cycles.
7:2
R/W 00h
Register Number: This field selects one register within a particular Bus, Device, and Function as specified by the other fields in the Configuration Address Register. This field is mapped to byte 7 [7:2] of the request header format during PCI Express Configuration cycles and A[7:2] during the DMI Configuration cycles.
1:0
Reserved
3.4.2
CONFIG_DATA--Configuration Data Register
I/O Address: Default Value: Access: Size: 0CFCh 00000000h R/W 32 bits
CONFIG_DATA is a 32-bit read/write window into configuration space. The portion of configuration space that is referenced by CONFIG_DATA is determined by the contents of CONFIG_ADDRESS.
Bit 31:0 Access & Default R/W 0000 0000h Description Configuration Data Window (CDW): If bit 31 of CONFIG_ADDRESS is 1, any I/O access to the CONFIG_DATA register will produce a configuration transaction using the contents of CONFIG_ADDRESS to determine the bus, device, function, and offset of the register to be accessed.
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Host Bridge/DRAM Controller Registers (D0:F0)
The DRAM Controller registers are in Device 0 (D0), Function 0 (F0). Warning: Address locations that are not listed are considered Reserved registers locations. Reads to Reserved registers may return non-zero values. Writes to reserved locations may cause system failures. All registers that are defined in the PCI 2.3 specification, but are not necessary or implemented in this component are not included in this document. The reserved/unimplemented space in the PCI configuration header space is not documented as such in this summary. Table 4-1. Device 0 Function 0 Register Address Map Summary
Address Offset 00h-01h 02h-03h 04h-05h 06h-07h 08h 09h-0Bh 0Ch 0Dh 0Eh 0Fh-2Bh 2Ch-2Dh 2Eh-2Fh 30h-33h 34h 35h-3Fh 40h-43h 44h-47h 48h-4Bh 4Ch-4Fh Register Symbol VID DID PCICMD PCISTS RID CC -- MLT HDR -- SVID SID -- CAPPTR -- EPBAR MCHBAR PCIEXBAR DMIBAR Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Class Code Reserved Master Latency Timer Header Type Reserved Subsystem Vendor Identification Subsystem Identification Reserved Capabilities Pointer Reserved Egress Port Base Address MCH Memory Mapped Register Range Base Address PCI Express* Register Range Base Address Root Complex Register Range Base Address Default Value 8086h 2580h 0006h 0090h 00h 060000h -- 00h 00h -- 0000h 0000h -- E0h -- 00000000h 00000000h E0000000 h 00000000h Access RO RO RO, R/W RO, R/W/C RO RO -- RO RO -- R/W/O R/W/O -- RO -- RO R/W R/W R/W
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Address Offset 52h-53h 54h-57h 58h-5Bh 5Ch 5Dh 5Fh-8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98-9Bh 9Ch 9Dh 9Eh 9F-C7h C8h-C9h CAh-CBh CCh--CDh CEh--CFh D0h-DBh DCh-DFh E0h-E8h
Register Symbol -- DEVEN DEAP DERRSYN DERRDST -- PAM0 PAM1 PAM2 PAM3 PAM4 PAM5 PAM6 LAC -- TOLUD SMRAM ESMRAMC -- ERRSTS ERRCMD SMICMD SCICMD -- SKPD CAPID0 Reserved Device Enable
Register Name
Default Value -- 00000019h 00000000h 00h 00h -- 00h 00h 00h 00h 00h 00h 00h 00h -- 08h 00h 00h -- 0000h 0000h 0000h 0000h -- 00000000h 000000000 001090009 h -- 00h 00h 00h 00h -- 00h 00h
Access -- R/W RO/S RO/S RO/S -- R/W R/W R/W R/W R/W R/W R/W R/W -- R/W RO, R/W/L RO, R/W/L -- RO, R/W/L R/W R/W R/W -- R/W RO
DRAM Error Address Pointer DRAM Error Syndrome DRAM Error Destination Reserved Programmable Attribute Map 0 Programmable Attribute Map 1 Programmable Attribute Map 2 Programmable Attribute Map 3 Programmable Attribute Map 4 Programmable Attribute Map 5 Programmable Attribute Map 6 Legacy Access Control Reserved Top of Low Usable DRAM System Management RAM Control Extended System Management RAM Control Reserved Error Status Error Command SMI Command SCI Command Reserved Scratchpad Data Capability Identifier
E9h-FFh 100h 101h 102h 103h 104h-107h 108h 109h
-- C0DRB0 C0DRB1 C0DRB2 C0DRB3 -- C0DRA0 C0DRA2
Reserved Channel A DRAM Rank Boundary Address 0 Channel A DRAM Rank Boundary Address 1 Channel A DRAM Rank Boundary Address 2 Channel A DRAM Rank Boundary Address 3 Reserved Channel A DRAM Rank 0,1 Attribute Channel A DRAM Rank 2,3 Attribute
-- R/W R/W R/W R/W -- R/W R/W
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Address Offset 10Ah-10Bh 10Ch 10Dh 10E-10F 110h-113h 114h-117h 118h-11Fh 120h-123h 124h-17Fh 180h 181h 182h 183h 184h-187h 188h 189h 18Ah-18Bh 18Ch 18Dh 18Eh-18Fh 190h-193h 194h 195h-19Fh 1A0h-1A3h 1A4h-F0Fh F10h-F13h F14h
Register Symbol -- C0DCLKDI S -- C0BNKAR C -- C0DRT1 -- C0DRC0 -- C1DRB0 C1DRB1 C1DRB2 C1DRB3 -- C1DRA0 C1DRA2 -- C1DCLKDI S -- C1BNKAR C -- C1DRT1 -- C1DRC0 -- PMCFG PMSTS Reserved
Register Name
Default Value -- 00h -- 0000h -- 900122h -- 00000000h -- 00h 00h 00h 00h -- 00h 00h -- 00h -- 0000h -- 900122h -- 00000000h -- 00000000h 00000000h
Access -- R/W -- R/W -- R/W -- R/W, RO -- R/W R/W R/W R/W -- R/W R/W -- R/W -- R/W -- R/W, RO -- R/W, RO -- R/W R/W/C/S
Channel A DRAM Clock Disable Reserved Channel A DRAM Bank Architecture Reserved Channel A DRAM Timing Register Reserved Channel A DRAM Controller Mode 0 Reserved Channel B DRAM Rank Boundary Address 0 Channel B DRAM Rank Boundary Address 1 Channel B DRAM Rank Boundary Address 2 Channel B DRAM Rank Boundary Address 3 Reserved Channel B DRAM Rank 0,1 Attribute Channel B DRAM Rank 2,3 Attribute Reserved Channel B DRAM Clock Disable Reserved Channel B Bank Architecture Reserved Channel B DRAM Timing Register 1 Reserved Channel B DRAM Controller Mode 0 Reserved Power Management Configuration Power Management Status
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4.1
Device 0 Function 0 PCI Configuration Register Details
VID--Vendor Identification (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 00h 8086h RO 16 bits
4.1.1
This register combined with the Device Identification register uniquely identifies any PCI device.
Bit 15:0 Access & Default RO 8086h Description Vendor Identification Number (VID): PCI standard identification for Intel.
4.1.2
DID--Device Identification (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 02h 2580h RO 16 bits
This register combined with the Vendor Identification register uniquely identifies any PCI device.
Bit 15:0 Access & Default RO 2580h Description Device Identification Number (DID): This field is an identifier assigned to the MCH core/primary PCI device.
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4.1.3
PCICMD--PCI Command (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 04h 0006h RO, R/W 16 bits
Since MCH Device 0 does not physically reside on Primary PCI bus, many of the bits are not implemented.
Bit 15:10 9 RO 0b R/W 0b Access & Default Reserved Fast Back-to-Back Enable (FB2B). This bit controls whether or not the master can do fast back-to-back write. Since device 0 is strictly a target this bit is not implemented and is hardwired to 0. SERR Enable (SERRE). This bit is a global enable bit for Device 0 SERR messaging. The MCH does not have a SERR signal. The MCH communicates the SERR condition by sending an SERR message over DMI to the ICH6. 1 = Enable. The MCH is enabled to generate SERR messages over DMI for specific Device 0 error conditions that are individually enabled in the ERRCMD register. The error status is reported in the ERRSTS, and PCISTS registers. If SERRE is clear, then the SERR message is not generated by the MCH for Device 0. 0 = Disable Note: That this bit only controls SERR messaging for the Device 0. Device 1 has its own SERRE bits to control error reporting for error conditions occurring in that device. The control bits are used in a logical OR manner to enable the SERR DMI message mechanism. 7 6 5 4 3 2 1 0 RO 0b RO 0b RO 0b RO 0b RO 0b RO 1b RO 1b RO 0b Address/Data Stepping Enable (ADSTEP). Hardwired to 0. Parity Error Enable (PERRE). PERR# is not implemented by the MCH and this bit is hardwired to 0. VGA Palette Snoop Enable (VGASNOOP). Hardwired to a 0. Memory Write and Invalidate Enable (MWIE). The MCH will never issue memory write and invalidate commands. This bit is therefore hardwired to 0. Reserved Bus Master Enable (BME). The MCH is always enabled as a master. This bit is hardwired to a 1. Memory Access Enable (MAE). The MCH always allows access to main memory. This bit is not implemented and is hardwired to 1. I/O Access Enable (IOAE). Hardwired to a 0. Description
8
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4.1.4
PCISTS--PCI Status (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 06h 0090h RO, R/W/C 16 bits
This status register reports the occurrence of error events on Device 0's PCI interface. Since the MCH Device 0 does not physically reside on Primary PCI, many of the bits are not implemented.
Bit 15 14 Access & Default RO 0b R/W/C 0b Description Detected Parity Error (DPE): Hhardwired to a 0. Signaled System Error (SSE): Software clears this bit by writing a 1 to it. 1 = The MCH Device 0 generated an SERR message over DMI for any enabled Device 0 error condition. Device 0 error conditions are enabled in the PCICMD, and ERRCMD registers. Device 0 error flags are read/reset from the PCISTS, or ERRSTS registers. Received Master Abort Status (RMAS): Software clears this bit by writing a 1 to it. 1 = MCH generated a DMI request that receives an Unsupported Request completion packet. 12 R/WC 0b Received Target Abort Status (RTAS): Software clears this bit by writing a 1 to it. 1 = MCH generated a DMI request that receives a Completer Abort completion packet. 11 RO 0b RO 00b RO 0b RO 1b Signaled Target Abort Status (STAS): The MCH will not generate a Target Abort DMI completion packet or Special Cycle. This bit is not implemented in the MCH and is hardwired to a 0. DEVSEL Timing (DEVT): These bits are hardwired to "00". Device 0 does not physically connect to Primary PCI. These bits are set to "00" (fast decode) so that optimum DEVSEL timing for Primary PCI is not limited by the MCH. Master Data Parity Error Detected (DPD): PERR signaling and messaging are not implemented by the MCH; therefore, this bit is hardwired to 0. Fast Back-to-Back (FB2B): Hardwired to 1. Device 0 does not physically connect to Primary PCI. This bit is set to 1 (indicating fast back-to-back capability) so that the optimum setting for Primary PCI is not limited by the MCH. Reserved RO 0b RO 1b 66 MHz Capable: Does not apply to PCI Express*. Hardwired to 0. Capability List (CLIST): This bit is hardwired to 1 to indicate to the configuration software that this device/function implements a list of new capabilities. A list of new capabilities is accessed via register CAPPTR at configuration address offset 34h. Register CAPPTR contains an offset pointing to the start address within configuration space of this device where the Capability standard register resides. Reserved
13
R/WC 0b
10:9
8 7
6 5 4
3:0
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4.1.5
RID--Revision Identification (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 08h 00h RO 8 bits
This register contains the revision number of the MCH Device 0.
Bit 7:0 Access & Default RO 00h Description Revision Identification Number (RID): This is an 8-bit value that indicates the revision identification number for the MCH Device 0. 05h = B-2 Stepping
4.1.6
CC--Class Code (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 09h 060000h RO 24 bits
This register identifies the basic function of the device, a more specific sub-class, and a registerspecific programming interface.
Bit 23:16 Access & Default RO 06h Description Base Class Code (BCC): This is an 8-bit value that indicates the base class code for the MCH. 06h = Bridge device. 15:8 RO 00h Sub-Class Code (SUBCC): This is an 8-bit value that indicates the category of Bridge into which the MCH falls. 00h = Host Bridge. 7:0 RO 00h Programming Interface (PI): This is an 8-bit value that indicates the programming interface of this device. This value does not specify a particular register set layout and provides no practical use for this device.
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4.1.7
MLT--Master Latency Timer (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 0Dh 00h RO 8 bits
Device 0 in the MCH is not a PCI master. Therefore this register is not implemented.
Bit 7:0 Access & Default Reserved Description
4.1.8
HDR--Header Type (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 0Eh 00h RO 8 bits
This register identifies the header layout of the configuration space. No physical register exists at this location.
Bit 7:0 Access & Default RO 00h Description PCI Header (HDR): This field always returns 0 to indicate that the MCH is a single function device with standard header layout.
4.1.9
SVID--Subsystem Vendor Identification (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 2Ch 0000h R/WO 16 bits
This value is used to identify the vendor of the subsystem.
Bit 15:0 Access & Default R/WO 0000h Description Subsystem Vendor ID (SUBVID): This field should be programmed during bootup to indicate the vendor of the system board. After it has been written once, it becomes read only.
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4.1.10
SID--Subsystem Identification (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 2Eh 0000h R/W/O 16 bits
This value is used to identify a particular subsystem.
Bit 15:0 Access & Default R/WO 0000h Description Subsystem ID (SUBID): This field should be programmed during BIOS initialization. After it has been written once, it becomes read only.
4.1.11
CAPPTR--Capabilities Pointer (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 34h E0h RO 8 bits
The CAPPTR provides the offset that is the pointer to the location of the first device capability in the capability list.
Bit 7:0 Access & Default RO E0h Description Pointer to the offset of the first capability ID register block: In this case the first capability is the product-specific Capability Identifier (CAPID0).
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4.1.12
EPBAR--Egress Port Base Address (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 40h 00000000h RO 32 bits
This is the base address for the Egress Port MMIO configuration space. There is no physical memory within this 4-KB window that can be addressed. The 4 KB reserved by this register does not alias to any PCI 2.3 compliant memory mapped space. On reset, this register is disabled and must be enabled by writing a 1 to EPBAREN[Dev 0, offset 54h, bit 27]
Bit 31:12 Access & Default R/W 00000h Description Egress Port MMIO Base Address: This field corresponds to bits 31 to 12 of the base address Egress Port MMIO configuration space. BIOS will program this register resulting in a base address for a 4-KB block of contiguous memory address space. This register ensures that a naturally aligned 4-KB space is allocated within total addressable memory space of 4 GB. System software uses this base address to program the MCH MMIO register set. 11:0 Reserved
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4.1.13
MCHBAR--MCH Memory Mapped Register Range Base Address (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 44h 00000000h R/W 32 bits
This is the base address for the MCH memory-mapped configuration space. There is no physical memory within this 16-KB window that can be addressed. The 16 KB reserved by this register does not alias to any PCI 2.3 compliant memory mapped space. On reset, this register is disabled and must be enabled by writing a 1 to MCHBAREN [Dev 0, offset 54h, bit 28]
Bit 31:14 Access & Default R/W 00000h Description MCH Memory Mapped Base Address: This field corresponds to bits 31 to 14 of the base address MCH memory-mapped configuration space. BIOS will program this register resulting in a base address for a 16-KB block of contiguous memory address space. This register ensures that a naturally aligned 16-KB space is allocated within total addressable memory space of 4 GB. System software uses this base address to program the MCH Memory-mapped register set. 13:0 Reserved
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4.1.14
PCIEXBAR--PCI Express* Register Range Base Address (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 48h E0000000h R/W 32 bits
This is the base address for the PCI Express configuration space. This window of addresses contains the 4 KB of configuration space for each PCI Express device that can potentially be part of the PCI Express hierarchy associated with the MCH. There is not actual physical memory within this 256-MB window that can be addressed. Each PCI Express hierarchies require a PCI Express BASE register. The MCH supports one PCI Express hierarchy. The 256 MB reserved by this register does not alias to any PCI 2.3 compliant memory-mapped space. For example, MCHBAR reserves a 16-KB space and reserves a 4-KB space both outside of PCIEXBAR space. They cannot be overlaid on the space reserved by PCIEXBAR for devices 0. On reset, this register is disabled and must be enabled by writing a 1 to PCIEXBAREN [Dev 0, offset 54h, bit 31] If the PCI Express Base Address [bits 31:28] were set to Fh, an overlap with the High BIOS area, APIC ranges would result. Software must guarantee that these ranges do not overlap. The PCI Express Base Address cannot be less than the maximum address written to the Top of physical memory register (TOLUD). If a system is populated with more than 3.5 GB, either the PCI Express Enhanced Access mechanism must be disabled or the value in TOLUD must be reduced to report that only 3.5 GB are present in the system to allow a value of Eh for the PCI Express Base Address (assuming that all PCI 2.3 compatible configuration space fits above 3.75 GB).
Bit 31:28
Access & Default R/W Eh
Description PCI Express* Base Address: This field corresponds to bits 31 to 28 of the base address for PCI Express enhanced configuration space. BIOS will program this register resulting in a base address for a 256-MB block of contiguous memory address space. Having control of those particular 4 bits insures that this base address will be on a 256-MB boundary, above the lowest 256 MB and still within total addressable memory space, currently 4 GB. The address used to access the PCI Express configuration space for a specific device can be determined as follows: PCI Express Base Address + Bus Number * 1 MB + Device Number * 32 KB + Function Number * 4 KB The address used to access the PCI Express configuration space for Device 1 in this component would be PCI Express Base Address + 0 * 1 MB + 1 * 32 KB + 0 * 4 KB = PCI Express Base Address + 32 KB. Remember that this address is the beginning of the 4-KB space that contains both the PCI compatible configuration space and the PCI Express extended configuration space.
27:0
Reserved
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4.1.15
DMIBAR--Root Complex Register Range Base Address (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 4Ch 00000000h R/W 32 bits
This is the base address for the Root Complex configuration space. This window of addresses contains the Root Complex Register set for the PCI Express hierarchy associated with the MCH. There is no physical memory within this 4-KB window that can be addressed. The 4 KB that is reserved by this register does not alias to any PCI 2.3 compliant memory mapped space. On reset, this register is disabled and must be enabled by writing a 1 to the DMIBAREN [Dev 0, offset 54h, bit 29]. |
Bit 31:12 Access & Default R/W 0000 0h Description DMI Base Address: This field corresponds to bits 31 to 12 of the base address DMI configuration space. BIOS will program this register resulting in a base address for a 4-KB block of contiguous memory address space. This register ensures that a naturally aligned 4-KB space is allocated within total addressable memory space of 4 GB. System software uses this base address to program the DMI register set. 11:0 Reserved
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4.1.16
DEVEN--Device Enable (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 54h 00000019h R/W 32 bits
This register allows for enabling/disabling of PCI devices and functions that are within the MCH.
Bit 31 Access & Default R/W 0b Description PCIEXBAR Enable (PCIEXBAREN): 0 = The PCIEXBAR register is disabled. Memory read and write transactions proceed as if there were no PCIEXBAR register. PCIEXBAR bits 31:28 are R/W with no functionality behind them. 1 = The PCIEXBAR register is enabled. Memory read and write transactions whose address bits 31:28 match PCIEXBAR 31:28 will be translated to configuration reads and writes within the MCH. These translated cycles are routed as shown in the table above. 30 29 R/W 0b Reserved DMIBAR Enable (DMIBAREN): 0 = DMIBAR is disabled and does not claim any memory. 1 = DMIBAR memory mapped accesses are claimed and decoded appropriately. 28 R/W 0b MCHBAR Enable (MCHBAREN): 0 = MCHBAR is disabled and does not claim any memory. 1 = MCHBAR memory mapped accesses are claimed and decoded appropriately. 27 R/W 0b EPBAR Enable (EPBAREN): 0 = EPBAR is disabled and does not claim any memory. 1 = EPBAR memory mapped accesses are claimed and decoded appropriately. 26:2 1 R/W 1b Strap dependent 0 RO 1b Reserved PCI Express* Port (D1EN): 0 = Bus 0 Device 1 Function 0 is disabled and hidden. This also gates PCI Express internal clock (lgclk) and asserts PCI Express internal reset (lgrstb). 1 = Bus 0 Device 1 Function 0 is enabled and visible. Host Bridge: Bus 0 Device 0 Function 0 can not be disabled and is therefore hardwired to 1.
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4.1.17
DEAP--DRAM Error Address Pointer (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 58h 00000000h RO/S 32 bits
This register contains the address of detected DRAM ECC error(s).
Bit 31:7 Access & Default RO/S 0000000h Description Error Address Pointer (EAP): This field is used to store the 128B (Two Cache Line) address of main memory for which an error (single bit or multi-bit error) has occurred. Note that the value of this bit field represents the address of the first single or the first multiple bit error occurrence after the error flag bits in the ERRSTS register have been cleared by software. A multiple bit error will overwrite a single bit error. Once the error flag bits are set as a result of an error, this bit field is locked and does not change as a result of a new error. These bits are reset on PWROK. 6:1 0 RO/S 0b Reserved Channel Indicator: This bit indicates which memory channel had the error. 0 = Channel A 1 = Channel B
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4.1.18
DERRSYN--DRAM Error Syndrome (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 5Ch 00h RO/S 8 bits
This register is used to report the ECC syndromes for each quad word of a 32B-aligned data quantity read from the DRAM array.
Bit 7:0 Access & Default RO/S 00h Description DRAM ECC Syndrome (DECCSYN): After a DRAM ECC error on any QW of the data chunk resulting from a read command, hardware loads this field with a syndrome that describes the set of bits associated with the first QW containing an error. Note that this field is locked from the time that it is loaded up to the time when the error flag is cleared by software. If the first error was a single bit, correctable error, then a subsequent multiple bit error on any of the QWs in this read transaction or any subsequent read transaction will cause the field to be rerecorded. When a multiple bit error is recorded, the field is locked until the error flag is cleared by software. In all other cases, an error that occurs after the first error, and before the error flag, has been cleared by software, will escape recording. These bits are reset on PWROK.
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4.1.19
DERRDST--DRAM Error Destination (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 5Dh 00h RO/S 8 bits
This register is used to report the destination of the data containing an ECC error whose address is recorded in DEAP register.
Bit 7:6 5:0 RO/S 00h Access & Default Reserved Error Source Code: This field is updated concurrently with DERRSYN. 00h = Processor to memory reads 01h-07h = Reserved 08h-09h = DMI VC0 initiated and targeting cycles/data 0Ah-0Bh = DMI VC1 initiated and targeting cycles/data 0Ch-0Dh = DMI VCp initiated and targeting cycles/data 0Eh-0Fh = Reserved 10h = PCI Express* initiated and targeting cycles/data 11h = Reserved 12h = PCI Express* initiated and targeting cycles/data 13h = Reserved 14h-16h = PCI Express* initiated and targeting cycles/data 17h = Reserved 18h-1Ah: = Reserved 1Bh-3Eh = Reserved 3Fh = Used for broadcast messages with data targeting multiple units. (e.g., EOI). These bits are reset on PWROK. Description
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4.1.20
PAM0--Programmable Attribute Map 0 (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 90h 00h R/W 8 bits
This register controls the read, write, and shadowing attributes of the BIOS area from 0F0000h- 0FFFFFh The MCH allows programmable memory attributes on 13 Legacy memory segments of various sizes in the 768-KB to 1-MB address range. Seven Programmable Attribute Map (PAM) Registers are used to support these features. Cache ability of these areas is controlled via the MTRR registers in the P6 processor. Two bits are used to specify memory attributes for each memory segment. These bits apply to both host accesses and PCI initiator accesses to the PAM areas. These attributes are: * RE (Read Enable). When RE = 1, the processor read accesses to the corresponding memory segment are claimed by the MCH and directed to main memory. Conversely, when RE = 0, the host read accesses are directed to Primary PCI. * WE (Write Enable). When WE = 1, the host write accesses to the corresponding memory segment are claimed by the MCH and directed to main memory. Conversely, when WE = 0, the host write accesses are directed to Primary PCI. The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write, or disabled. For example, if a memory segment has RE = 1 and WE = 0, the segment is Read Only. Each PAM Register controls two regions, typically 16 KB in size.
Bit 7:6 5:4 R/W 00b Access & Default Reserved 0F0000-0FFFFF Attribute (HIENABLE): This field controls the steering of read and write cycles that addresses the BIOS area from 0F0000h to 0FFFFFh. 00 = DRAM Disabled: All accesses are directed to the DMI. 01 = Read Only: All reads are sent to DRAM. All writes are forwarded to the DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. 3:0 Reserved Description
Warning: The MCH may hang if a PCI Express graphics attach or DMI originated access to Read Disabled or Write Disabled PAM segments occurs (due to a possible IWB to non-DRAM). For these reasons the following critical restriction is placed on the programming of the PAM regions: At the time that a DMI or PCI Express graphics attach accesses to the PAM region may occur, the targeted PAM segment must be programmed to be both readable and writeable.
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4.1.21
PAM1--Programmable Attribute Map 1 (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 91h 00h R/W 8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from 0C0000h- 0C7FFFh.
Bit 7:6 5:4 R/W 00b Access & Default Reserved 0C4000-0C7FFF Attribute (HIENABLE): This field controls the steering of read and write cycles that address the BIOS area from 0C4000h to 0C7FFFh. 00 = DRAM Disabled: Accesses are directed to the DMI. 01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. 3:2 1:0 R/W 00b Reserved 0C0000-0C3FFF Attribute (LOENABLE): This field controls the steering of read and write cycles that address the BIOS area from 0C0000h to 0C3FFFh. 00 = DRAM Disabled: Accesses are directed to the DMI. 01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. Description
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4.1.22
PAM2--Programmable Attribute Map 2 (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 92h 00h R/W 8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from 0C8000h- 0CFFFFh.
Bit 7:6 5:4 R/W 00b Access & Default Reserved 0CC000h-0CFFFFh Attribute (HIENABLE): 00 = DRAM Disabled: Accesses are directed to the DMI. 01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. 3:2 1:0 R/W 00b Reserved 0C8000h-0CBFFFh Attribute (LOENABLE): This field controls the steering of read and write cycles that address the BIOS area from 0C8000h to 0CBFFFh. 00 = DRAM Disabled: Accesses are directed to the DMI. 01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. Description
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4.1.23
PAM3--Programmable Attribute Map 3 (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 93h 00h R/W 8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from 0D0000h- 0D7FFFh.
Bit 7:6 5:4 R/W 00b Access & Default Reserved 0D4000h-0D7FFFh Attribute (HIENABLE): This field controls the steering of read and write cycles that address the BIOS area from 0D4000h to 0D7FFFh. 00 = DRAM Disabled: Accesses are directed to the DMI. 01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. 3:2 1:0 R/W 00b Reserved 0D0000h-0D3FFFh Attribute (LOENABLE): This field controls the steering of read and write cycles that address the BIOS area from 0D0000h to 0D3FFFh. 00 = DRAM Disabled: Accesses are directed to the DMI. 01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. Description
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4.1.24
PAM4--Programmable Attribute Map 4 (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 94h 00h R/W 8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from 0D8000h0DFFFFh.
Bit 7:6 5:4 R/W 00b Access & Default Reserved 0DC000h-0DFFFFh Attribute (HIENABLE): This field controls the steering of read and write cycles that address the BIOS area from 0DC000h to 0DFFFFh. 00 = DRAM Disabled: Accesses are directed to the DMI. 01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. 3:2 1:0 R/W 00b Reserved 0D8000h-0DBFFFh Attribute (LOENABLE): This field controls the steering of read and write cycles that address the BIOS area from 0D8000h to 0DBFFFh. 00 = DRAM Disabled: Accesses are directed to the DMI. 01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. Description
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4.1.25
PAM5--Programmable Attribute Map 5 (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 95h 00h R/W 8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from 0E0000h0E7FFFh.
Bit 7:6 5:4 R/W 00b Access & Default Reserved 0E4000h-0E7FFFh Attribute (HIENABLE): This field controls the steering of read and write cycles that address the BIOS area from 0E4000h to 0E7FFFh. 00 = DRAM Disabled: Accesses are directed to the DMI. 01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. 3:2 1:0 R/W 00b Reserved 0E0000h-0E3FFFh Attribute (LOENABLE): This field controls the steering of read and write cycles that address the BIOS area from 0E0000h to 0E3FFFh. 00 = DRAM Disabled: Accesses are directed to the DMI. 01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. Description
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4.1.26
PAM6--Programmable Attribute Map 6 (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 96h 00h R/W 8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from 0E8000h- 0EFFFFh.
Bit 7:6 5:4 R/W 00b Access & Default Reserved 0EC000h-0EFFFFh Attribute (HIENABLE): This field controls the steering of read and write cycles that address the BIOS area from 0E4000h to 0E7FFFh. 00 = DRAM Disabled: Accesses are directed to the DMI. 01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. 3:2 1:0 R/W 00b Reserved 0E8000h-0EBFFFh Attribute (LOENABLE): This field controls the steering of read and write cycles that address the BIOS area from 0E0000h to 0E3FFFh. 00 = DRAM Disabled: Accesses are directed to the DMI. 01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. Description
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4.1.27
LAC--Legacy Access Control (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 97h 00h R/W 8 bits
This 8-bit register controls a fixed DRAM hole from 15-16 MB.
Bit 7 Access & Default R/W 0b Description Hole Enable (HEN): This field enables a memory hole in DRAM space. The DRAM that lies "behind" this space is not remapped. 0 = No memory hole. 1 = Memory hole from 15 MB to 16 MB. 6:1 0 R/W 0b Reserved MDA Present (MDAP): This bit works with the VGA Enable bits in the BCTRL register of Device 1 to control the routing of processor initiated transactions targeting MDA compatible I/O and memory address ranges. This bit should not be set if device 1's VGA Enable bit is not set. If device 1's VGA enable bit is not set, then accesses to I/O address range x3BCh- x3BFh are forwarded to the DMI. If the VGA enable bit is set and MDA is not present, then accesses to I/O address range x3BCh-x3BFh are forwarded to PCI Express* if the address is within the corresponding IOBASE and IOLIMIT, otherwise they are forwarded to the DMI. MDA resources are defined as the following: Memory: I/O: 0B0000h - 0B7FFFh 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh, (Including ISA address aliases, A [15:10] are not used in decode)
Any I/O reference that includes the I/O locations listed above, or their aliases, will be forwarded to the DMI even if the reference includes I/O locations not listed above. The following table shows the behavior for all combinations of MDA and VGA: VGAEN 0 0 1 1 MDAP 0 1 0 1 Description All References to MDA and VGA space are routed to the DMI Illegal combination All VGA and MDA references are routed to PCI Express Graphics Attach. All VGA references are routed to PCI Express Graphics Attach. MDA references are routed to the DMI
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Host Bridge/DRAM Controller Registers (D0:F0)
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4.1.28
TOLUD--Top of Low Usable DRAM (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 9Ch 08h R/W 8 bits
This 8-bit register defines the Top of Low Usable DRAM. TSEG and Graphics Stolen Memory are within the DRAM space defined.
Bit 7:3 Access & Default R/W 01h Description Top of Low Usable DRAM (TOLUD): This register contains bits 31 to 27 of an address one byte above the maximum DRAM memory that is usable by the operating system. Address bits 31 down to 27 programmed to 01h implies a minimum memory size of 128 MBs. Configuration software must set this value to the smaller of the following 2 choices: * Maximum amount memory in the system plus one byte or the minimum address allocated for PCI memory. Address bits 26:0 are assumed to be 000_0000h for the purposes of address comparison. The host interface positively decodes an address towards DRAM if the incoming address is less than the value programmed in this register. If this register is set to 0000 0b, it implies 128 MBs of system memory. 2:0 Reserved
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4.1.29
SMRAM--System Management RAM Control (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 9Dh 00h R/W/L, RO 8 bits
The SMRAMC register controls how accesses to Compatible and Extended SMRAM spaces are treated. The Open, Close, and Lock bits function only when G_SMRAME bit is set to a 1. Also, the OPEN bit must be reset before the LOCK bit is set.
Bit 7 6 R/W/L 0b Access & Default Reserved SMM Space Open (D_OPEN): When D_OPEN=1 and D_LCK=0, the SMM space DRAM is made visible even when SMM decode is not active. This is intended to help BIOS initialize SMM space. Software should ensure that D_OPEN=1 and D_CLS=1 are not set at the same time. SMM Space Closed (D_CLS): When D_CLS = 1 SMM space DRAM is not accessible to data references, even if SMM decode is active. Code references may still access SMM space DRAM. This will allow SMM software to reference through SMM space to update the display even when SMM is mapped over the VGA range. Software should ensure that D_OPEN=1 and D_CLS=1 are not set at the same time. Note that the D_CLS bit only applies to Compatible SMM space. SMM Space Locked (D_LCK): When D_LCK is set to 1, D_OPEN is reset to 0 and D_LCK, D_OPEN, C_BASE_SEG, H_SMRAM_EN, TSEG_SZ and TSEG_EN become read only. D_LCK can be set to 1 via a normal configuration space write but can only be cleared by a full Reset. The combination of D_LCK and D_OPEN provide convenience with security. The BIOS can use the D_OPEN function to initialize SMM space and then use D_LCK to "lock down" SMM space in the future so that no application software (or BIOS itself) can violate the integrity of SMM space, even if the program has knowledge of the D_OPEN function. Global SMRAM Enable (G_SMRAME): If set to a 1, Compatible SMRAM functions are enabled, providing 128 KB of DRAM accessible at the A0000h address while in SMM (ADSB with SMM decode). To enable Extended SMRAM function this bit has be set to 1. Refer to the section on SMM for more details. Once D_LCK is set, this bit becomes read only. Compatible SMM Space Base Segment (C_BASE_SEG): This field indicates the location of SMM space. SMM DRAM is not remapped. It is simply made visible if the conditions are right to access SMM space, otherwise the access is forwarded to DMI. Since the MCH supports only the SMM space between A0000h and BFFFFh, this field is hardwired to 010. Description
5
R/W/L 0b
4
R/W/L 0b
3
R/W/L 0b
2:0
RO 010b
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4.1.30
ESMRAMC--Extended System Management RAM Control (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 9Eh 00h R/W/L, RO 8 bits
The Extended SMRAM register controls the configuration of Extended SMRAM space. The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory space that is above 1 MB.
Bit 7 Access & Default R/W/L 0b Description Enable High SMRAM (H_SMRAME): This bit controls the SMM memory space location (i.e., above 1 MB or below 1 MB) When G_SMRAME is 1 and H_SMRAME is 1, the high SMRAM memory space is enabled. SMRAM accesses within the range 0FEDA0000h to 0FEDBFFFFh are remapped to DRAM addresses within the range 000A0000h to 000BFFFFh. Once D_LCK has been set, this bit becomes read only. Invalid SMRAM Access (E_SMERR): This bit is set when the processor has accessed the defined memory ranges in Extended SMRAM (High Memory and T-segment) while not in SMM space and with the D-OPEN bit = 0. It is software's responsibility to clear this bit. The software must write a 1 to this bit to clear it. SMRAM Cacheable (SM_CACHE): This bit is forced to 1 by the MCH . L1 Cache Enable for SMRAM (SM_L1): This bit is forced to 1 by the MCH. L2 Cache Enable for SMRAM (SM_L2): This bit is forced to 1 by the MCH. Reserved R/W/L 0b TSEG Enable (T_EN): This bit Enables SMRAM memory for Extended SMRAM space only. When G_SMRAME =1 and TSEG_EN = 1, the TSEG is enabled to appear in the appropriate physical address space. Note that once D_LCK is set, this bit becomes read only.
6
R/W/C 0b
5 4 3 2:1 0
RO 1b RO 1b RO 1b
4.1.31
ERRSTS--Error Status (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 C8h 0000h R/WC/S, RO 16 bits
This register is used to report various error conditions via the SERR DMI messaging mechanism. An SERR DMI message is generated on a zero to one transition of any of these flags (if enabled by the ERRCMD and PCICMD registers). These bits are set regardless of whether or not the SERR is enabled and generated. After the error processing is complete, the error logging mechanism can be unlocked by clearing the appropriate status bit by software writing a 1 to it.
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0Bit 15:13 12
Access & Default Reserved R/WC/S 0b R/WC/S 0b
Description
MCH Software Generated Event for SMI: 1 = This bit indicates the source of the SMI was a Device 2 Software Event. MCH Thermal Sensor Event for SMI/SCI/SERR: This bit indicates that a MCH Thermal Sensor trip has occurred and an SMI, SCI, or SERR has been generated. The status bit is set only if a message is sent based on Thermal event enables in Error command, SMI command, and SCI command registers. A trip point can generate one of SMI, SCI, or SERR interrupts (two or more per event is illegal). Multiple trip points can generate the same interrupt, if software chooses this mode, subsequent trips may be lost. If this bit is already set, an interrupt message will not be sent on a new thermal sensor event. Reserved
11
10 9 R/WC/S 0b
LOCK to non-DRAM Memory Flag (LCKF): 1 = MCH detected a lock operation to memory space that did not map into DRAM. Received Refresh Timeout Flag(RRTOF): 1 = 1024 memory core refreshes are enqueued. DRAM Throttle Flag (DTF): 1 = Indicates that a DRAM Throttling condition occurred. 0 = Software has cleared this flag since the most recent throttling event
8
R/WC/S 0b R/WC/S 0b
7
6:2 1 R/WC/S 0b
Reserved Multiple-bit DRAM ECC Error Flag (DMERR): If this bit is set to 1, a memory read data transfer had an uncorrectable multiple-bit error. When this bit is set, the address, channel number, and device number that caused the error are logged in the EAP register. Once this bit is set, the EAP, CN, DN, and ES fields are locked until the processor clears this bit by writing a 1. Software uses bits [1:0] to detect whether the logged error address is for Single or Multiple-bit error. This bit is reset on PWROK.
0
R/WC/S 0b
Single-bit DRAM ECC Error Flag (DSERR): If this bit is set to 1, a memory read data transfer had a single-bit correctable error and the corrected data was sent for the access. When this bit is set the address and device number that caused the error are logged in the EAP register. Once this bit is set the EAP, CN, DN, and ES fields are locked to further single bit error updates until the processor clears this bit by writing a 1. A multiple bit error that occurs after this bit is set will overwrite the EAP, CN, and DN fields with the multiple-bit error signature and the MEF bit will also be set. This bit is reset on PWROK.
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4.1.32
ERRCMD--Error Command (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 CAh 0000h R/W 16 bits
This register controls the MCH responses to various system errors. Since the MCH does not have an SERR# signal, SERR messages are passed from the MCH to the Intel ICH6 over DMI. When a bit in this register is set, a SERR message will be generated on DMI when the corresponding flag is set in the ERRSTS register. The actual generation of the SERR message is globally enabled for Device 0 via the PCI Command register.
Bit 15:12 11 R/W 0b Access & Default Reserved SERR on MCH Thermal Sensor Event (TSESERR) 1 = The MCH generates a DMI SERR special cycle when bit 11 of the ERRSTS is set. The SERR must not be enabled at the same time as the SMI for the same thermal sensor event. 0 = Reporting of this condition via SERR messaging is disabled. 10 9 R/W 0b Reserved SERR on LOCK to non-DRAM Memory (LCKERR) 1 = The MCH will generate a DMI SERR special cycle whenever a processor lock cycle is detected that does not hit DRAM. 0 = Reporting of this condition via SERR messaging is disabled. 8 R/W 0b SERR on DRAM Refresh Timeout (DRTOERR) 1 = The MCH generates a DMI SERR special cycle when a DRAM Refresh timeout occurs. 0 = Reporting of this condition via SERR messaging is disabled. 7:2 1 R/W 0b Reserved SERR Multiple-Bit DRAM ECC Error (DMERR) 1 = The MCH generates a SERR message over DMI when it detects a multiplebit error reported by the DRAM controller. 0 = Reporting of this condition via SERR messaging is disabled. For systems not supporting ECC, this bit must be disabled. 0 R/W 0b SERR on Single-bit ECC Error (DSERR) 1 = The MCH generates a SERR special cycle over DMI when the DRAM controller detects a single bit error. 0 = Reporting of this condition via SERR messaging is disabled. For systems that do not support ECC, this bit must be disabled. Description
Intel 82925X MCH Datasheet
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4.1.33
SMICMD--SMI Command (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 CCh 0000h R/W 16 bits
This register enables various errors to generate an SMI DMI special cycle. When an error flag is set in the ERRSTS register, it can generate an SERR, SMI, or SCI DMI special cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers, respectively. Note that one and only one message type can be enabled.
Bit 15:2 1 R/W 0b Access & Default Description
Reserved SMI on Multiple-Bit DRAM ECC Error (DMESMI): 1 = The MCH generates an SMI DMI message when it detects a multiple-bit error reported by the DRAM controller. 0 = Reporting of this condition via SMI messaging is disabled. For systems not supporting ECC, this bit must be disabled.
0
R/W 0b
SMI on Single-bit ECC Error (DSESMI): 1 = The MCH generates an SMI DMI special cycle when the DRAM controller detects a single bit error. 0 = Reporting of this condition via SMI messaging is disabled. For systems that do not support ECC, this bit must be disabled.
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Host Bridge/DRAM Controller Registers (D0:F0)
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4.1.34
SCICMD--SCI Command (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 CEh 0000h R/W 16 bits
This register enables various errors to generate an SMI DMI special cycle. When an error flag is set in the ERRSTS register, it can generate an SERR, SMI, or SCI DMI special cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers, respectively. Note that one and only one message type can be enabled.
Bit 15:2 1 R/W 0b Access & Default Reserved SCI on Multiple-Bit DRAM ECC Error (DMESCI): 1 = The MCH generates an SCI DMI message when it detects a multiple-bit error reported by the DRAM controller. 0 = Reporting of this condition via SCI messaging is disabled. For systems not supporting ECC this bit must be disabled. 0 R/W 0b SCI on Single-bit ECC Error (DSESCI): 1 = The MCH generates an SCI DMI special cycle when the DRAM controller detects a single bit error. 0 = Reporting of this condition via SCI messaging is disabled. For systems that do not support ECC this bit must be disabled. Description
4.1.35
SKPD--Scratchpad Data (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 DCh 00000000h R/W 32 bits
This register holds 32 writable bits with no functionality behind them. It is for the convenience of BIOS and graphics drivers.
Bit 31:0 Access & Default R/W 00000000 h Description Scratchpad Data: 1 DWord of data storage.
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4.1.36
CAPID0--Capability Identifier (D0:F0)
PCI Device: Address Offset: Default Value: Access: Size: 0 E0h 000000000001090009h RO 72 bits
Bit 71:28 27:24 23:16 15:8 7:0
Access & Default Reserved RO 1h RO 09h RO 00h RO 09h
Description
CAPID Version: This field has the value 0001b to identify the first revision of the CAPID register definition. CAPID Length: This field has the value 09h to indicate the structure length (9 bytes). Next Capability Pointer: This field is hardwired to 00h indicating the end of the capabilities linked list. CAP_ID: This field has the value 1001b to identify the CAP_ID assigned by the PCI SIG for vendor dependent capability pointers.
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MCHBAR Registers
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5
MCHBAR Registers
These registers are offset from the MCHBAR base address.
Address Offset 100h 101h 102h 103h 104-107h 108h 109h 10A-10Bh 10Ch 10Dh 10E-10F 110-113h 114-117h 118-11Fh 120-123h 124-17Fh 180h 181h 182h 183h 184-187h 188h 189h 18A-18Bh 18Ch Register Symbol C0DRB0 C0DRB1 C0DRB2 C0DRB3 -- C0DRA0 C0DRA2 -- C0DCLKDIS -- C0BNKARC -- C0DRT1 -- C0DRC0 -- C1DRB0 C1DRB1 C1DRB2 C1DRB3 -- C1DRA0 C1DRA2 -- C1DCLKDIS Register Name Channel A DRAM Rank Boundary Address 0 Channel A DRAM Rank Boundary Address 1 Channel A DRAM Rank Boundary Address 2 Channel A DRAM Rank Boundary Address 3 Reserved Channel A DRAM Rank 0,1 Attribute Channel A DRAM Rank 2,3 Attribute Reserved Channel A DRAM Clock Disable Reserved Channel A DRAM Bank Architecture Reserved Channel A DRAM Timing Register Reserved Channel A DRAM Controller Mode 0 Reserved Channel B DRAM Rank Boundary Address 0 Channel B DRAM Rank Boundary Address 1 Channel B DRAM Rank Boundary Address 2 Channel B DRAM Rank Boundary Address 3 Reserved Channel B DRAM Rank 0,1 Attribute Channel B DRAM Rank 2,3 Attribute Reserved Channel B DRAM Clock Disable Default Value 00h 00h 00h 00h -- 00h 00h -- 00h -- 0000h -- 900122h -- 00000000h -- 00h 00h 00h 00h -- 00h 00h -- 00h Access R/W R/W R/W R/W -- R/W R/W -- R/W -- R/W -- R/W -- R/W, RO -- R/W R/W R/W R/W -- R/W R/W -- R/W
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MCHBAR Registers
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Address Offset 18Dh 18E-18Fh 190-193h 194h 195-19Fh 1A0-1A3h 1A4-F0Fh F10-F13h F14h
Register Symbol -- C1BNKARC -- C1DRT1 -- C1DRC0 -- PMCFG PMSTS Reserved
Register Name
Default Value -- 0000h -- 900122h -- 00000000h -- 00000000h 00000000h
Access -- R/W -- R/W, RO -- R/W, RO -- R/W R/W/C/S
Channel B Bank Architecture Reserved Channel B DRAM Timing Register 1 Reserved Channel B DRAM Controller Mode 0 Reserved Power Management Configuration Power Management Status
5.1
5.1.1
MCHBAR Register Details
C0DRB0--Channel A DRAM Rank Boundary Address 0
MMIO Range: Address Offset: Default Value: Access: Size: MCHBAR 100h 00h R/W 8 bits
The DRAM Rank Boundary Register defines the upper boundary address of each DRAM rank with a granularity of 32 MB. Each rank has its own single-byte DRB register. These registers are used to determine which chip select will be active for a given address. Channel and Rank Map: Channel A Rank 0: Channel A Rank 1: Channel A Rank 2: Channel A Rank 3: Channel B Rank 0: Channel B Rank 1: Channel B Rank 2: Channel B Rank 3: 100h 101h 102h 103h 180h 181h 182h 183h
Single Channel or Asymmetric Channels Example
If the channels are independent, addresses in Channel B should begin where addresses in Channel A left off, and the address of the first rank of Channel A can be calculated from the technology (256 Mbit, 512 Mbit, or 1 Gbit) and the x8 or x16 configuration. With independent channels, a value of 01h in C0DRB0 indicates that 32 MB of DRAM has been populated in the first rank, and the top address in that rank is 32 MB.
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Programming guide If Channel A is empty, all of the C0DRBs are programmed with 00h. C0DRB0 = Total memory in chA rank0 (in 32-MB increments) C0DRB1 = Total memory in chA rank0 + chA rank1 (in 32-MB increments) ______ C1DRB0 = Total memory in chA rank0 + chA rank1 + chA rank2 + chA rank3 + chB rank0 (in 32-MB increments) If Channel B is empty, all of the C1DRBs are programmed with the same value as C0DRB3.
Interleaved Channels Example
If channels are interleaved, corresponding ranks in opposing channels will contain the same value, and the value programmed takes into account the fact that twice as many addresses are spanned by this rank compared to the single channel case. With interleaved channels, a value of 01h in C0DRB0 and a value of 01h in C1DRB0 indicate that 32 MB of DRAM has been populated in the first rank of each channel and the top address in that rank of either channel is 64 MB. Programming guide: C0DRB0 = C1DRB0 = Total memory in chA rank0 (in 32-MB increments) C0DRB1 = C1DRB1 = Total memory in chA rank0 + chA rank1 (in 32-MB increments) ______ C0DRB3 = C1DRB3 = Total memory in chA rank0 + chA rank1+ chA rank2 + chA rank3 (in 32-MB increments) Note: Channel A DRB3 and Channel B DRB3 must be equal for this mode, but the other DRBs may be different. In all modes, if a DIMM is single sided, it appears as a populated rank and an empty rank. A DRB must be programmed appropriately for each. Each Rank is represented by a byte. Each byte has the following format.
Bit 7:0
Access & Default R/W 00h
Description Channel A DRAM Rank Boundary Address: This 8 bit value defines the upper and lower addresses for each DRAM rank. Bits 6:2 are compared against Address 31:27 to determine the upper address limit of a particular rank. Bits 1:0 must be 0s. Bit 7 may be programmed to a 1 in the highest DRB (DRB3) if 4 GBs of memory is present.
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5.1.2
C0DRB1--Channel A DRAM Rank Boundary Address 1
MMIO Range: Address Offset: Default Value: Access: Size: MCHBAR 101h 00h R/W 8 bits
The operation of this register is detailed in the description for register C0DRB0.
5.1.3
C0DRB2--Channel A DRAM Rank Boundary Address 2
MMIO Range: Address Offset: Default Value: Access: Size: MCHBAR 102h 00h R/W 8 bits
The operation of this register is detailed in the description for register C0DRB0.
5.1.4
C0DRB3--Channel A DRAM Rank Boundary Address 3
MMIO Range: Address Offset: Default Value: Access: Size: MCHBAR 103h 00h R/W 8 bits
The operation of this register is detailed in the description for register C0DRB0.
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5.1.5
C0DRA0--Channel A DRAM Rank 0,1 Attribute
MMIO Range: Address Offset: Default Value: Access: Size: MCHBAR 108h 00h R/W 8 bits
The DRAM Rank Attribute Registers define the page sizes to be used when accessing different ranks. These registers should be left with their default value (all zeros) for any rank that is unpopulated, as determined by the corresponding CxDRB registers. Each byte of information in the CxDRA registers describes the page size of a pair of ranks. Channel and Rank Map: Channel A Rank 0, 1: Channel A Rank 2, 3: Channel B Rank 0, 1: Channel B Rank 2, 3:
Bit 7 6:4 R/W 000b Access & Default Reserved Channel A DRAM odd Rank Attribute: This 3 bit field defines the page size of the corresponding rank. 000 = Unpopulated 001 = Reserved 010 = 4 KB 011 = 8 KB 100 = 16 KB Others = Reserved 3 2:0 R/W 000b Reserved Channel A DRAM even Rank Attribute: This 3 bit field defines the page size of the corresponding rank. 000 = Unpopulated 001 = Reserved 010 = 4 KB 011 = 8 KB 100 = 16 KB Others = Reserved
108h 109h 188h 189h
Description
5.1.6
C0DRA2--Channel A DRAM Rank 2,3 Attribute
MMIO Range: Address Offset: Default Value: Access: Size: MCHBAR 109h 00h R/W 8 bits
The operation of this register is detailed in the description for register C0DRA0.
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5.1.7
C0DCLKDIS--Channel A DRAM Clock Disable
MMIO Range: Address Offset: Default Value: Access: Size: MCHBAR 10Ch 00h R/W 8 bits
This register can be used to disable the system memory clock signals to each DIMM slot. This can significantly reduce EMI and Power concerns for clocks that go to unpopulated DIMMs. Clocks should be enabled based on whether a slot is populated, and what kind of DIMM is present.
Bit 7:6 5 R/W 0b Access & Default Reserved DIMM Clock Gate Enable Pair 5 0 = Tri-state the corresponding clock pair. 1 = Enable the corresponding clock pair. DIMM Clock Gate Enable Pair 4 0 = Tri-state the corresponding clock pair. 1 = Enable the corresponding clock pair. DIMM Clock Gate Enable Pair 3 0 = Tri-state the corresponding clock pair. 1 = Enable the corresponding clock pair. DIMM Clock Gate Enable Pair 2 0 = Tri-state the corresponding clock pair. 1 = Enable the corresponding clock pair. DIMM Clock Gate Enable Pair 1 0 = Tri-state the corresponding clock pair. 1 = Enable the corresponding clock pair. DIMM Clock Gate Enable Pair 0 0 = Tri-state the corresponding clock pair. 1 = Enable the corresponding clock pair. Description
4
R/W 0b
3
R/W 0b
2
R/W 0b
1
R/W 0b
0
R/W 0b
Note: Since there are multiple clock signals assigned to each Rank of a DIMM, it is important to clarify exactly which Rank width field affects which clock signal:
Channel 0 0 1 1
Rank 0 or 1 2 or 3 0 or 1 2 or 3
Clocks Affected SCLK_A[2:0]/ SCLK_A[2:0]# SCLK_A[5:3]/ SCLK_A[5:3]# SCLK_B[2:0]/ SCLK_B[2:0]# SCLK_B[5:3]/ SCLK_B[5:3]#
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5.1.8
C0BNKARC--Channel A DRAM Bank Architecture
MMIO Range: Address Offset: Default Value: Access: Size: MCHBAR 10Eh 0000h R/W 16 bits
This register is used to program the bank architecture for each Rank.
Bit 15:8 7:6 R/W 00b Access & Default Reserved Rank 3 Bank Architecture 00 = 4 Bank. 01 = 8 Bank. 1X = Reserved 5:4 R/W 00b Rank 2 Bank Architecture 00 = 4 Bank. 01 = 8 Bank. 1X = Reserved 3:2 R/W 00b Rank 1 Bank Architecture 00 = 4 Bank. 01 = 8 Bank. 1X = Reserved 1:0 R/W 00b Rank 0 Bank Architecture 00 = 4 Bank. 01 = 8 Bank. 1X = Reserved Description
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5.1.9
C0DRT1--Channel A DRAM Timing Register
MMIO Range: Address Offset: Default Value: Access: Size:
Bit 31:24 23:20 R/W 9h Access & Default Reserved Activate to Precharge delay (tRAS). This bit controls the number of DRAM clocks for tRAS. Minimum recommendations are beside their corresponding encodings. 0h - 3h = Reserved 4h - Fh = Four to Fifteen Clocks respectively. 19 RO 0b Reserved for Activate to Precharge Delay (tRAS) MAX: It is required that the Panic Refresh timer be set to a value less than the tRAS maximum. Based on this setting, a Panic Refresh occurs before TRAS maximum expiration and closes all the banks. This bit controls the maximum number of clocks that a DRAM bank can remain open. After this time period, the DRAM controller will guarantee to pre-charge the bank. This time period may or may not be set to overlap with time period that requires a refresh to happen. The DRAM controller includes a separate tRAS-MAX counter for every supported bank. With a maximum of four ranks, and four banks per rank, there are 16 counters per channel. 0 = 120 microseconds 1 = Reserved Note: This register will become Read Only with a value of 0 if the design does not implement these counters. tRAS-MAX is not required because a panic refresh will close all banks in a rank before tRAS-MAX expires. 18:10 9:8 R/W 01b Reserved CASB Latency (tCL). This value is programmable on DDR2 DIMMs. The value programmed here must match the CAS Latency of every DDR2 DIMM in the system. Encoding 00 01 10 11 7 Reserved DDR2 CL 5 4 3 Reserved
MCHBAR 114h 900122hh R/W, RO 32 bits
Description
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Bit 6:4
Access & Default R/W 010b
Description DRAM RAS to CAS Delay (tRCD). This bit controls the number of clocks inserted between a row activate command and a read or write command to that row. 000 = 2 DRAM clocks 001 = Reserved 010 = 4 DRAM clocks 011 = 5 DRAM clocks 100 - 111 = Reserved
3 2:0 R/W 010b
Reserved DRAM RAS Precharge (tRP). This bit controls the number of clocks that are inserted between a row precharge command and an activate command to the same rank. 000 = 2 DRAM clocks 001 = Reserved 010 = 4 DRAM clocks 011 = 5 DRAM clocks 100 - 111 = Reserved
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5.1.10
C0DRC0--Channel A DRAM Controller Mode 0
MMIO Range: Address Offset: Default Value: Access: Size: MCHBAR 120h 00000000h R/W 32 bits
Bit 31:30 29
Access & Default Reserved R/W 0b
Description
Initialization Complete (IC): This bit is used for communication of software state between the memory controller and the BIOS. BIOS sets this bit to 1 after initialization of the DRAM memory array is complete. Reserved
28:11 10:8 R/W 000b
Refresh Mode Select (RMS): This field determines whether refresh is enabled and, if so, at what rate refreshes will be executed. 000 = Refresh disabled 001 = Refresh enabled. Refresh interval 15.6 usec 010 = Refresh enabled. Refresh interval 7.8 usec 011 = Refresh enabled. Refresh interval 3.9 usec 100 = Refresh enabled. Refresh interval 1.95 usec 111 = Refresh enabled. Refresh interval 64 clocks (fast refresh mode) Other = Reserved
7
RO 0b
Reserved
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Bit 6:4
Access & Default R/W 000 b
Description Mode Select (SMS). These bits select the special operational mode of the DRAM interface. The special modes are intended for initialization at power up. 000 = Post Reset state - When the MCH exits reset (power-up or otherwise), the mode select field is cleared to "000". During any reset sequence, while power is applied and reset is active, the MCH de-asserts all CKE signals. After internal reset is de-asserted, CKE signals remain de-asserted until this field is written to a value different than "000". On this event, all CKE signals are asserted. During suspend, MCH internal signal triggers DRAM controller to flush pending commands and enter all ranks into Self-Refresh mode. As part of resume sequence, MCH will be reset - which will clear this bit field to "000" and maintain CKE signals de-asserted. After internal reset is deasserted, CKE signals remain de-asserted until this field is written to a value different than "000". On this event, all CKE signals are asserted. During entry to other low power states (C3, S1), MCH internal signal triggers DRAM controller to flush pending commands and enter all ranks into Self-Refresh mode. During exit to normal mode, MCH signal triggers DRAM controller to exit Self-Refresh and resume normal operation without S/W involvement. 001 = NOP Command Enable - All processor cycles to DRAM result in a NOP command on the DRAM interface. 010 = All Banks Pre-charge Enable - All processor cycles to DRAM result in an "all banks precharge" command on the DRAM interface. 011 = Mode Register Set Enable - All processor cycles to DRAM result in a "mode register" set command on the DRAM interface. Host address lines are mapped to DRAM address lines in order to specify the command sent. Host address lines [12:3] are mapped to MA[9:0], and HA[13] is mapped to MA[11]. 101 = Reserved 110 = CBR Refresh Enable - In this mode all processor cycles to DRAM result in a CBR cycle on the DRAM interface 111 = Normal operation
3:2 1:0 RO
Reserved DRAM Type (DT). This field is used to select between supported SDRAM types. This bit is controlled by the MTYPE strap signal. 00 = Reserved 01 = Reserved 10 = Second Revision Dual Data Rate (DDR2) SDRAM 11 = Reserved
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5.1.11
C1DRB0--Channel B DRAM Rank Boundary Address 0
MMIO Range: Address Offset: Default Value: Access: Size: MCHBAR 180h 00h R/W 8 bits
The operation of this register is detailed in the description for register C0DRB0.
5.1.12
C1DRB1--Channel B DRAM Rank Boundary Address 1
MMIO Range: Address Offset: Default Value: Access: Size: MCHBAR 181h 00h R/W 8 bits
The operation of this register is detailed in the description for register C0DRB0.
5.1.13
C1DRB2--Channel B DRAM Rank Boundary Address 2
MMIO Range: Address Offset: Default Value: Access: Size: MCHBAR 182h 00h R/W 8 bits
The operation of this register is detailed in the description for register C0DRB0.
5.1.14
C1DRB3--Channel B DRAM Rank Boundary Address 3
MMIO Range: Address Offset: Default Value: Access: Size: MCHBAR 183h 00h R/W 8 bits
The operation of this register is detailed in the description for register C0DRB0.
5.1.15
C1DRA0--Channel B DRAM Rank 0,1 Attribute
MMIO Range: Address Offset: Default Value: Access: Size: MCHBAR 188h 00h R/W 8 bits
The operation of this register is detailed in the description for register C0DRA0.
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5.1.16
C1DRA2--Channel B DRAM Rank 2,3 Attribute
MMIO Range: Address Offset: Default Value: Access: Size: MCHBAR 189h 00h R/W 8 bits
The operation of this register is detailed in the description for register C0DRA0.
5.1.17
C1DCLKDIS--Channel B DRAM Clock Disable
MMIO Range: Address Offset: Default Value: Access: Size: MCHBAR 18Ch 00h R/W 8 bits
The operation of this register is detailed in the description for register C0DCLKDIS.
5.1.18
C1BNKARC--Channel B Bank Architecture
MMIO Range: Address Offset: Default Value: Access: Size: MCHBAR 18Eh 0000h R/W 16 bits
The operation of this register is detailed in the description for register C0BNKARC.
5.1.19
C1DRT1--Channel B DRAM Timing Register 1
MMIO Range: Address Offset: Default Value: Access: Size: MCHBAR 194h 900122h R/W 32 bits
The operation of this register is detailed in the description for register C0DRT1.
5.1.20
C1DRC0--Channel B DRAM Controller Mode 0
MMIO Range: Address Offset: Default Value: Access: Size: MCHBAR 1A0h 00000000h R/W 32 bits
The operation of this register is detailed in the description for register C0DRC0.
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5.1.21
PMCFG--Power Management Configuration
MMIO Range: Address Offset: Default Value: Access: Size: MCHBAR F10h 00000000h R/W 32 bits
Bit 31:5 4
Access & Default Reserved R/W 0b
Description
Enhanced Power Management Features Enable 0 = Legacy power management mode 1 = Reserved.
3:0
Reserved
5.1.22
PMSTS--Power Management Status
MMIO Range: Address Offset: Default Value: Access: Size: This register is Reset by PWROK only.
Bit 31:2 1 R/WC/S 0b Access & Default Reserved Channel B in self-refresh. This bit is set by power management hardware after Channel B is placed in self refresh as a result of a Power State or a Reset Warn sequence. It is cleared by power management hardware before starting Channel B self refresh exit sequence initiated by a power management exit. It is cleared by BIOS in a warm reset (Reset# asserted while pwrok is asserted) exit sequence. 0 = Channel B not guaranteed to be in self-refresh. 1 = Channel B in Self-Refresh. 0 R/WC/S 0b Channel A in Self-refresh. Set by power management hardware after Channel A is placed in self refresh as a result of a Power State or a Reset Warn sequence. It is cleared by power management hardware before starting Channel A self refresh exit sequence initiated by a power management exit. It is cleared by the BIOS in a warm reset (Reset# asserted while PWOK is asserted) exit sequence. 0 = Channel A not guaranteed to be in self-refresh. 1 = Channel A in Self-Refresh. Description
MCHBAR F14h 00000000h R/W 32 bits
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EPBAR Registers--Egress Port Register Summary
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6
EPBAR Registers--Egress Port Register Summary
These registers are offset from the EPBAR base address. Table 6-1. Egress Port Register Address Map
Address Offset 044h-047h 050h-053h 058h- 05Fh 060h-063h 068h- 06Fh Register Symbol EPESD EPLE1D EPLE1A EPLE2D EPLE2A Register Name EP Element Self Description EP Link Entry 1 Description EP Link Entry 1 Address EP Link Entry 2 Description EP Link Entry 2 Address Default Value 0000h 0100h 000000000 0000000h 02000002h 000000000 0008000h Access R/WO, RO R/WO, RO R/WO, RO R/WO, RO RO
6.1
EP RCRB Configuration Register Details
Figure 6-1. Link Declaration Topology
(G)MCH
X16
PEG (Port #2)
Link #2 (Type 1)
Link #1 (Type 0)
Egress Port (Port #0)
Main Memory Subsystem
Link #2 (Type 0) Link #1 (Type 0) DMI (Port #1)
Link #1 (Type 0)
X4
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Egress Port (Port #0)
Egress_LinkDeclar_Topo
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6.1.1
EPESD--EP Element Self Description
MMIO Range: Address Offset: Default Value: Access: Size: EPBAR 044h 00000201h R/WO, RO 32 bits
This register provides information about the root complex element containing this Link Declaration capability.
Bit Access & Default RO 00h R/WO 00h Description
31:24
Port Number: This field specifies the port number associated with this element with respect to the component that contains this element. A value of 00h indicates to configuration software that this is the default egress port. Component ID: This field identifies the physical component that contains this Root Complex Element. Component IDs start at 1. This value is a mirror of the value in the Component ID field of all elements in this component. The value only needs to be written in one of the mirrored fields and it will be reflected everywhere that it is mirrored.
23:16
15:8
RO 02h
Number of Link Entries: This field indicates the number of link entries following the Element Self Description. This field reports 2 (one each for PCI Express* x16 Graphics Interface and DMI). Reserved
7:4 3:0 RO 1h
Element Type: This field Indicates the type of the Root Complex Element. 1h = Port to system memory
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6.1.2
EPLE1D--EP Link Entry 1 Description
MMIO Range: Address Offset: Default Value: Access: Size: EPBAR 050h 0100h R/WO, RO 32 bits
This register provides the First part of a Link Entry that declares an internal link to another Root Complex Element.
Bit Access & Default RO 01h R/WO 00h Description
31:24
Target Port Number: This field specifies the port number associated with the element targeted by this link entry (DMI). The target port number is with respect to the component that contains this element as specified by the target component ID. Target Component ID: This field identifies the physical or logical component that is targeted by this link entry. A value of 0 is reserved; Component IDs start at 1. This value is a mirror of the value in the Component ID field of all elements in this component. The value only needs to be written in one of the mirrored fields and it will be reflected everywhere that it is mirrored.
23:16
15:2 1 0 RO 0b R/WO 0b
Reserved Link Type: This bit indicates that the link points to memory-mapped space (for RCRB). The link address specifies the 64-bit base address of the target RCRB. Link Valid 0 = Link Entry is not valid and will be ignored. 1 = Link Entry specifies a valid link.
6.1.3
EPLE1A--EP Link Entry 1 Address
MMIO Range: Address Offset: Default Value: Access: Size: EPBAR 058h 0000000000000000h R/WO 64 bits
This register provides the second part of a Link Entry, which declares an internal link to another Root Complex Element.
Bit 63:32 31:12 11:0 R/WO 0 0000h Access & Default Reserved Link Address: This field provides the memory-mapped base address of the RCRB that is the target element (DMI) for this link entry. Reserved Description
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6.1.4
EPLE2D--EP Link Entry 2 Description
MMIO Range: Address Offset: Default Value: Access: Size: EPBAR 060h 02000002h R/WO, RO 32 bits
This register provides the First part of a Link Entry that declares an internal link to another Root Complex Element.
Bit 31:24 Access & Default RO 02h Description Target Port Number: This field specifies the port number associated with the element targeted by this link entry (PCI Express* x16 Graphics Interface). The target port number is with respect to the component that contains this element as specified by the target component ID. Target Component ID: This field identifies the physical or logical component that is targeted by this link entry. A value of 0 is reserved; Component IDs start at 1. This value is a mirror of the value in the Component ID field of all elements in this component. The value only needs to be written in one of the mirrored fields and it will be reflected everywhere that it is mirrored. 15:2 1 RO 1b Reserved Link Type: 1 = Link points to configuration space of the integrated device that controls the x16 root port. The link address specifies the configuration address (segment, bus, device, function) of the target root port. Link Valid 0 = Link Entry is not valid and will be ignored. 1 = Link Entry specifies a valid link.
23:16
R/WO 00h
0
R/WO 0b
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6.1.5
EPLE2A--EP Link Entry 2 Address
MMIO Range: Address Offset: Default Value: Access: Size: EPBAR 068h 0000000000008000h RO 64 bits
This register provides the second part of a Link Entry that declares an internal link to another Root Complex Element.
Bit 63:28 27:20 19:15 14:12 11:0 RO 00h RO 0 0001b RO 000b Access & Default Reserved Bus Number Device Number: Target for this link is PCI Express* x16 port (Device 1). Function Number Reserved Description
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DMIBAR Registers--Direct Media Interface (DMI) RCRB
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7
DMIBAR Registers--Direct Media Interface (DMI) RCRB
This Root Complex Register Block (RCRB) controls the MCH-Intel ICH6 serial interconnect. The base address of this space is programmed in DMIBAR in device 0 configuration space. These registers are offset from the DMIBAR base address Table 7-1. DMI Register Address Map Summary
Address offset 000-003h 004-007h 008-00Bh 00C-00Dh 00E-00Fh 010-013h 014-017h 018-019h 01A-01Bh 01C-01Fh 020-023h 024-025h 026-027h 028-083h 084-087h 088-089h 08A-08Bh 08C-FFFh Register Symbol DMIVCECH DMIPVCCAP1 DMIPVCCAP2 DMIPVCCTL -- DMIVC0RCAP DMIVC0RCTL -- DMIVC0RSTS DMIVC1RCAP DMIVC1RCTL -- DMIVC1RSTS -- DMILCAP DMILCTL DMILSTS -- Register Name DMI Virtual Channel Enhanced Capability Header DMI Port VC Capability Register 1 DMI Port VC Capability Register 2 DMI Port VC Control Reserved DMI VC0 Resource Capability DMI VC0 Resource Control Reserved DMI VC0 Resource Status DMI VC1 Resource Capability DMI VC1 Resource Control Reserved DMI VC1 Resource Status Reserved DMI Link Capabilities DMI Link Control DMI Link Status Reserved PCI Dev # DMIBAR DMIBAR DMIBAR DMIBAR DMIBAR DMIBAR DMIBAR DMIBAR DMIBAR DMIBAR DMIBAR DMIBAR DMIBAR DMIBAR DMIBAR DMIBAR DMIBAR DMIBAR
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DMIBAR Registers--Direct Media Interface (DMI) RCRB
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7.1
7.1.1
Direct Media Interface (DMI) RCRB Register Details
DMIVCECH--DMI Virtual Channel Enhanced Capability Header
MMIO Range: Address Offset: Default Value: Access: Size: DMIBAR 000h 04010002h RO 32 bits
This register indicates DMI Virtual Channel capabilities.
Bit 31:20 19:16 15:0 Access & Default RO 040h RO 1h RO 0002h Description Pointer to Next Capability: This field indicates the next item in the list. Capability Version: This field indicates support as a version 1 capability structure. Capability ID: This field indicates this is the Virtual Channel capability item.
7.1.2
DMIPVCCAP1--DMI Port VC Capability Register 1
MMIO Range: Address Offset: Default Value: Access: Size: DMIBAR 004h 00000001h R/WO, RO 32 bits
This register describes the configuration of Virtual Channels associated with this port.
Bit 31:12 11:10 9:8 RO 00b RO 00b Access & Default Reserved Port Arbitration Table Entry Size (PATS): This field indicates the size of the port arbitration table is 4 bits (to allow up to 8 ports). Reference Clock (RC) Fixed at 100 ns. Reserved RO 000b Low Priority Extended VC Count (LPEVC): This field indicates that there are no additional VCs of low priority with extended capabilities. Reserved R/WO 001b Extended VC Count: This field indicates that there is one additional VC (VC1) that exists with extended capabilities. Description
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DMIBAR Registers--Direct Media Interface (DMI) RCRB
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7.1.3
DMIPVCCAP2--DMI Port VC Capability Register 2
MMIO Range: Address Offset: Default Value: Access: Size: DMIBAR 008h 00000001h RO 32 bits
This register describes the configuration of Virtual Channels associated with this port.
Bit 31:24 23:8 7:0 RO 01h Access & Default RO 00h Description VC Arbitration Table Offset (ATO): This field indicates that no table is present for VC arbitration since it is fixed. Reserved VC Arbitration Capability: This field indicates that the VC arbitration is fixed in the root complex. VC1 is highest priority and VC0 is lowest priority.
7.1.4
DMIPVCCTL--DMI Port VC Control
MMIO Range: Address Offset: Default Value: Access: Size: DMIBAR 00Ch 00000000h R/W, RO 16 bits
Bit 15:4 3:1
Access & Default Reserved R/W 000b RO 0b
Description
VC Arbitration Select: This field indicates which VC should be programmed in the VC arbitration table. The root complex takes no action on the setting of this field since there is no arbitration table. Load VC Arbitration Table (LAT): This field indicates that the table programmed should be loaded into the VC arbitration table. This bit is defined as read/write with always returning 0 on reads.
0
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DMIBAR Registers--Direct Media Interface (DMI) RCRB
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7.1.5
DMIVC0RCAP--DMI VC0 Resource Capability
MMIO Range: Address Offset: Default Value: Access: Size: DMIBAR 010h 00000001h RO 32 bits
Bit 31:24 23 22:16 15 14 13:8 7:0
Access & Default RO 00h
Description Port Arbitration Table Offset (AT): This VC implements no port arbitration table since the arbitration is fixed. Reserved
RO 00h RO 0b RO 0b
Maximum Time Slots (MTS): This VC implements fixed arbitration, and therefore this field is not used. Reject Snoop Transactions (RTS): This VC must be able to take snoopable transactions. Advanced Packet Switching (APS): This VC is capable of all transactions, not just advanced packet switching transactions. Reserved
RO 01h
Port Arbitration Capability (PAC): This field indicates that this VC uses fixed port arbitration.
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DMIBAR Registers--Direct Media Interface (DMI) RCRB
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7.1.6
DMIVC0RCTL0--DMI VC0 Resource Control
MMIO Range: Address Offset: Default Value: Access: Size: DMIBAR 014h 8000007Fh R/W, RO 32 bits
This register controls the resources associated with PCI Express Virtual Channel 0.
Bit 31 30:27 26:24 23:20 19:17 R/W 0h RO 0b RO 000b Access & Default RO 1b Description Virtual Channel Enable (EN): Enables the VC when set. Disables the VC when cleared. Reserved Virtual Channel Identifier (ID): Indicates the ID to use for this virtual channel. Reserved Port Arbitration Select (PAS): Indicates which port table is being programmed. The root complex takes no action on this setting since the arbitration is fixed and there is no arbitration table. Load Port Arbitration Table (LAT): The root complex does not implement an arbitration table for this virtual channel. Reserved R/W 7Fh Transaction Class / Virtual Channel Map (TVM): This field indicates which transaction classes are mapped to this virtual channel. When a bit is set, this transaction class is mapped to the virtual channel. Reserved
16 15:8 7:1
0
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DMIBAR Registers--Direct Media Interface (DMI) RCRB
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7.1.7
DMIVC0RSTS--DMI VC0 Resource Status
MMIO Range: Address Offset: Default Value: Access: Size: DMIBAR 01Ah 00000002h RO 16 bits
This register reports the Virtual Channel specific status.
Bit 15:2 1 RO 1b Access & Default Reserved VC Negotiation Pending (NP): 0 = Virtual channel is Not being negotiated with ingress ports. 1 = Virtual channel is still being negotiated with ingress ports. 0 RO 0b Port Arbitration Tables Status (ATS): There is no port arbitration table for this VC, so this bit is reserved at 0. Description
7.1.8
DMIVC1RCAP--DMI VC1 Resource Capability
MMIO Range: Address Offset: Default Value: Access: Size:
Bit 31:24 Access & Default RO 00h
DMIBAR 01Ch 00008001h RO 32 bits
Description Port Arbitration Table Offset (AT): This field indicates the location of the port arbitration table in the root complex. A value of 3h indicates the table is at offset 30h. Reserved
23 22:16 15 14 13:8 7:0 RO 01h RO 00h RO 1b RO 0b
Maximum Time Slots (MTS): This value is updated by platform BIOS based upon the determination of the number of time slots available in the platform. Reject Snoop Transactions (RTS): All snoopable transactions on VC1 are rejected. This VC is for isochronous transfers only. Advanced Packet Switching (APS): This VC is capable of all transactions, not just advanced packet switching transactions. Reserved Port Arbitration Capability (PAC): This field indicates the port arbitration capability is time-based WRR of 128 phases.
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DMIBAR Registers--Direct Media Interface (DMI) RCRB
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7.1.9
DMIVC1RCTL1--DMI VC1 Resource Control
MMIO Range: Address Offset: Default Value: Access: Size: DMIBAR 020h 00100000h R/W, RO 32 bits
This register controls the resources associated with Virtual Channel 1.
Bit 31 Access & Default R/W 0b Virtual Channel Enable (EN): 0 = Disable. 1 = Enable. 30:27 26:24 23:20 19:17 R/W 0h RO 0b RO 0h R/W 001b Reserved Virtual Channel Identifier (ID): This field indicates the ID to use for this virtual channel. Reserved Port Arbitration Select (PAS): This field indicates which port table is being programmed. The only permissible value of this field is 4h for the time-based WRR entries. Load Port Arbitration Table (LAT): When set, the port arbitration table is loaded based upon the PAS field in this register. This bit always returns 0 when read. Reserved R/W 00h Transaction Class / Virtual Channel Map (TVM): This field indicates which transaction classes are mapped to this virtual channel. When a bit is set, this transaction class is mapped to the virtual channel. Reserved Description
16 15:8 7:1
0
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DMIBAR Registers--Direct Media Interface (DMI) RCRB
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7.1.10
DMIVC1RSTS--DMI VC1 Resource Status
MMIO Range: Address Offset: Default Value: Access: Size: DMIBAR 026h 0000h RO 16 bits
This register reports the Virtual Channel specific status.
Bit 15:2 1 RO 0b Access & Default Reserved VC Negotiation Pending (NP): 0 = Virtual channel is Not being negotiated with ingress ports. 1 = Virtual channel is still being negotiated with ingress ports. 0 RO 0b Port Arbitration Tables Status (ATS): This bit indicates the coherency status of the port arbitration table. 1 = LAT (offset 000Ch:bit 0) is written with value 1 and PAS (offset 0014h:bits19:17) has value of 4h. 0 = This bit is cleared after the table has been updated. Description
7.1.11
DMILCAP--DMI Link Capabilities
MMIO Range: Address Offset: Default Value: Access: Size: DMIBAR 084h 00012C41h R/WO, RO 32 bits
This register indicates DMI specific capabilities.
Bit 31:18 17:15 14:12 11:10 9:4 3:0 R/WO 010b R/WO 010b RO 11b RO 4h RO 1h Access & Default Reserved L1 Exit Latency (EL1). L1 not supported on DMI. L0s Exit Latency (EL0): This field indicates that exit latency is 128 ns to less than 256 ns. Active State Link PM Support (APMS): This field indicates that L0s is supported on DMI. Maximum Link Width (MLW): This field indicates the maximum link width is 4 ports. Maximum Link Speed (MLS): This field indicates the link speed is 2.5 Gb/s. Description
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7.1.12
DMILCTL--DMI Link Control
MMIO Range: Address Offset: Default Value: Access: Size: This register allows control of DMI.
Bit 15:8 7 R/W 0h Access & Default Reserved Extended Synch (ES): 1 = Forces extended transmission of FTS ordered sets when exiting L0s prior to entering L0 and extra TS1 sequences at exit from L1 prior to entering L0. Reserved R/W 00b Active State Link PM Control (APMC): Indicates whether DMI should enter L0s. 00 = Disabled 01 = L0s entry enabled 10 = Reserved 11 = Reserved Description
DMIBAR 088h 0000h R/W 16 bits
6:2 1:0
7.1.13
DMILSTS--DMI Link Status
MMIO Range: Address Offset: Default Value: Access: Size: This register indicates DMI status.
Bit 15:10 9:4 RO 00h Access & Default Reserved Negotiated Link Width (NLW): This field is valid only when the link is in the L0, L0s, or L1 states (after link width negotiation is successfully completed). Negotiated link width is x4 (000100b). All other encodings are reserved. 3:0 RO 1h Link Speed (LS) Link is 2.5 Gb/s. Description
DMIBAR 08Ah 0001h RO 16 bits
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Host-PCI Express* Graphics Bridge Registers (D1:F0)
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8
Host-PCI Express* Graphics Bridge Registers (D1:F0)
Device 1contains the controls associated with the PCI Express x16 root port that is the intended to attach as the point for external graphics. It is typically referred to as PCI Express* x16 Graphics Interface port. In addition, it also functions as the virtual PCI-to-PCI bridge. Warning: When reading the PCI Express "conceptual" registers such as this, you may not get a valid value unless the register value is stable. The PCI Express* Specification defines two types of reserved bits: Reserved and Preserved: * Reserved for future R/W implementations; software must preserve value read for writes to bits. * Reserved and Zero: Reserved for future R/WC/S implementations; software must use 0 for writes to bits. Unless explicitly documented as Reserved and Zero, all bits marked as reserved are part of the Reserved and Preserved type that have historically been the typical definition for Reserved. It is important to note that most (if not all) control bits in this device cannot be modified unless the link is down. Software is required to first Disable the link, then program the registers, and then reenable the link (which will cause a full-retrain with the new settings). Table 8-1. Host-PCI Express* Graphics Bridge Register Address Map (D1:F0)
Address Offset 00-01h 02-03h 04-05h 06-07h 08h 09-0Bh 0Ch 0Dh 0Eh 0F-17h 18h 19h 1Ah 1Bh Register Symbol VID1 DID1 PCICMD1 PCISTS1 RID1 CC1 CL1 -- HDR1 -- PBUSN1 SBUSN1 SUBUSN1 -- Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Class Code Cache Line Size Reserved Header Type Reserved Primary Bus Number Secondary Bus Number Subordinate Bus Number Reserved Default Value 8086h 2581h 0000h 0000h 00h 060400h 00h -- 01h -- 00h 00h 00h -- Access RO RO RO, R/W RO, R/W RO RO R/W -- RO -- RO RO R/W --
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Address Offset 1Ch 1Dh 1Eh-1Fh 20-21h 22-23h 24-25h 26-27h 28-33h 34h 35-3Bh 3Ch 3Dh 3E-3Fh 40-7Fh 80-83h
Register Symbol IOBASE1 IOLIMIT1 SSTS1 MBASE1 MLIMIT1 PMBASE1 PMLIMIT1 -- CAPPTR1 -- INTRLINE1 INTRPIN1 BCTRL1 -- PM_CAPID1
Register Name I/O Base Address I/O Limit Address Secondary Status Memory Base Address Memory Limit Address Prefetchable Memory Base Address Prefetchable Memory Limit Address Reserved Capabilities Pointer Reserved Interrupt Line Interrupt Pin Bridge Control Reserved Power Management Capabilities
Default Value F0h 00h 00h FFF0h 0000h FFF0h 0000h -- 88h -- 00h 00h 0000h -- 19029001h or 1902A001h 00000000h 0000800Dh 00008086h A005h 0000h 00000000h 0000h -- 0010h 0141h 00000000h 0000h 0000h 02012E01h 0000h 1001h 00000000h 01C0h 0X00h 0000h --
Access RO R/W RO, R/W/C R/W R/W RO, R/W RO, R/W -- RO -- R/W RO RO, R/W -- RO
84-87h 88-8Bh 8C-8Fh 90-91h 92-93h 94-97h 98-99h 9A-9Fh A0-A1h A2-A3h A4-A7h A8-A9h AA-ABh AC-AFh B0-B1h B2-B3h B4-B7h B8-B9h BA-BBh BC-BDh BE-BFh
PM_CS1 SS_CAPID SS MSI_CAPID MC MA MD -- PEG_CAPL PEG_CAP DCAP DCTL DSTS LCAP LCTL LSTS SLOTCAP SLOTCTL SLOTSTS RCTL --
Power Management Control/Status Subsystem ID and Vendor ID Capabilities Subsystem ID and Subsystem Vendor ID Message Signaled Interrupts Capability ID Message Control Message Address Message Data Reserved PCI Express* Capability List PCI Express Capabilities Device Capabilities Device Control Device Status Link Capabilities Link Control Link Status Slot Capabilities Slot Control Slot Status Root Control Reserved
RO, R/W/S RO RO RO RO, R/W RO, R/W R/W -- RO RO RO R/W RO R/WO RO, R/W RO R/WO R/W RO, R/W/C R/W --
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Address Offset C0-C3h C4-EBh EC-EFh F0-FFh 100-103h 104-107h 108-10Bh 10C-10Dh 10E-10Fh 110-113h 114-117h 118-119h 11A-11Bh 11C-11Fh 120-123h 124-125h 126-127h 128-13Fh 140-143h 144-147h 148-14Fh 150-153h 154-157h 158-15Fh 160-217h 218-21Fh 220-FFFh
Register Symbol RSTS -- PEGLC -- VCECH PVCCAP1 PVCCAP2 PVCCTL -- VC0RCAP VC0RCTL -- VC0RSTS VC1RCAP VC1RCTL -- VC1RSTS -- RCLDECH ESD -- LE1D -- LE1A -- PEGSSTS -- Root Status Reserved
Register Name
Default Value 00000000h -- 00000000h -- 14010002h 00000001h 00000001h 0000h -- 00000000h 8000007Fh -- 0000h 00008000h 01000000h -- 0000h -- 00010005h 02000100h -- 00000000h -- 000000000 0000000h -- 000000000 0000FFFh --
Access RO, R/W/C -- R/W, RO -- RO RO, R/WO RO R/W -- RO RO, R/W -- RO RO RO, R/W -- RO -- RO RO, R/WO -- RO, R/WO -- R/WO -- RO --
PCI Express*-Graphics Legacy Control Reserved Virtual Channel Enhanced Capability Header Port VC Capability Register 1 Port VC Capability Register 2 Port VC Control Reserved VC0 Resource Capability VC0 Resource Control Reserved VC0 Resource Status VC1 Resource Capability VC1 Resource Control Reserved VC1 Resource Status Reserved Root Complex Link Declaration Enhanced Capability Header Element Self Description Reserved Link Entry 1 Description Reserved Link Entry 1 Address Reserved PCI Express*-Graphics Sequence Status Reserved
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8.1
8.1.1
Device 1 Configuration Register Details
VID1--Vendor Identification (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 00h 8086h RO 16 bits
This register combined with the Device Identification register uniquely identifies any PCI device.
Bit 15:0 Access & Default RO 8086h Description Vendor Identification (VID1): PCI standard identification for Intel.
8.1.2
DID1--Device Identification (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 02h 2581h RO 16 bits
This register combined with the Vendor Identification register uniquely identifies any PCI device.
Bit 15:0 Access & Default RO 2581h Description Device Identification Number (DID1): This field is an identifier assigned to the MCH device 1 (virtual PCI-to-PCI bridge, PCI Express* Graphics port).
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8.1.3
PCICMD1--PCI Command (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size:
Bit 15:11 10 R/W 0b Access & Default Reserved INTA Assertion Disable: 0 = This device is permitted to generate INTA interrupt messages. 1 = This device is prevented from generating interrupt messages. Any INTA emulation interrupts already asserted must be de-asserted when this bit is set. Only affects interrupts generated by the device (PCI INTA from a PME or Hot Plug event) controlled by this command register. It does not affect upstream MSIs, upstream PCI INTA-INTD asserts and de-assert messages. 9 8 RO 0b R/W 0b Fast Back-to-Back Enable (FB2B): Not Applicable or Implemented. Hardwired to 0. SERR Message Enable (SERRE1): This bit is an enable bit for Device 1 SERR messaging. The MCH communicates the SERRB condition by sending an SERR message to the Intel(R) ICH6. This bit, when set, enables reporting of non-fatal and fatal errors to the Root Complex. Note that errors are reported if enabled either through this bit or through the PCI Express* specific bits in the Device Control Register 0 = The SERR message is generated by the MCH for Device 1 only under conditions enabled individually through the Device Control Register. 1 = The MCH is enabled to generate SERR messages which will be sent to the ICH6 for specific Device 1 error conditions that are individually enabled in the BCTRL1 register and for all non-fatal and fatal errors generated on the primary side of the virtual PCI to PCI Express bridge (not those received by the secondary side). The error status is reported in the PCISTS1 register. 7 6 R/WO 0b Reserved Parity Error Enable (PERRE): This bit controls whether or not the Master Data Parity Error bit in the PCI Status register can bet set. 0 = Master Data Parity Error bit in PCI Status register cannot be set. 1 = Master Data Parity Error bit in PCI Status register can be set. 5 4 3 RO 0b RO 0b RO 0b VGA Palette Snoop: Hardwired to 0. Memory Write and Invalidate Enable (MWIE): Hardwired to 0. Special Cycle Enable (SCE): Hardwired to 0.
1 04h 0000h RO, R/W 16 bits
Description
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Bit 2
Access & Default R/W 0b
Description Bus Master Enable (BME): This bit does not affect forwarding of completions from the primary interface to the secondary interface. 0 = This device is prevented from making memory or I/O requests to its primary bus. Note that according to the PCI specification, as MSI interrupt messages are in-band memory writes, disabling the bus master enable bit prevents this device from generating MSI interrupt messages or passing them from its secondary bus to its primary bus. Upstream memory writes/reads, I/O writes/reads, peer writes/reads, and MSIs will all be treated as illegal cycles. Writes are forwarded to memory address 0h with byte enables de-asserted. Reads will be forwarded to memory address 0h and will return Unsupported Request status (or Master abort) in its completion packet. 1 = This device is allowed to issue requests to its primary bus. Completions for previously issued memory read requests on the primary bus will be issued when the data is available.
1
R/W 0b
Memory Access Enable (MAE) 0 = All of device 1's memory space is disabled. 1 = Enable the Memory and Pre-fetchable memory address ranges defined in the MBASE1, MLIMIT1, PMBASE1, and PMLIMIT1 registers.
0
R/W 0b
IO Access Enable (IOAE) 0 = All of device 1's I/O space is disabled. 1 = Enable the I/O address range defined in the IOBASE1 and IOLIMIT1 registers.
8.1.4
PCISTS1--PCI Status (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 06h 0000h RO, R/W/C 16 bits
This register reports the occurrence of error conditions associated with primary side of the "virtual" Host-PCI Express bridge in the MCH.
Bit 15 14 Access & Default RO 0b R/WC 0b Description Detected Parity Error (DPE): Hardwired to 0. Parity (generating poisoned TLPs) is not supported on the primary side of this device. Signaled System Error (SSE): 1 = This bit is set when this Device sends an SERR due to detecting an ERR_FATAL or ERR_NONFATAL condition and the SERR Enable bit in the Command register is `1'. Both received (if enabled by BCTRL1[1]) and internally detected error messages do not affect this field. Received Master Abort Status (RMAS): Not Applicable or Implemented. Hardwired to 0. The concept of a master abort does not exist on primary side of this device.
13
RO 0b
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Bit 12 11 10:9
Access & Default RO 0b RO 0b RO 00b RO 0b
Description Received Target Abort Status (RTAS): Hardwired to 0. The concept of a target abort does not exist on primary side of this device. Signaled Target Abort Status (STAS): Hardwired to 0. The concept of a target abort does not exist on primary side of this device. DEVSELB Timing (DEVT): This device is not the subtractive decoded device on bus 0. This bit field is therefore hardwired to 00 to indicate that the device uses the fastest possible decode. Master Data Parity Error (PMDPE): Because the primary side of the PCI Express* x16 Graphics Interface's virtual PCI-to-PCI bridge is integrated with the MCH functionality, there is no scenario where this bit will get set. Because hardware will never set this bit, it is impossible for software to have an opportunity to clear this bit or otherwise test that it is implemented. The PCI specification defines it as a R/WC; however, for this implementation, an RO definition behaves the same way and will meet all Microsoft testing requirements. This bit can only be set when the Parity Error Enable bit in the PCI Command register is set.
8
7 6 5 4 3
RO 0b
Fast Back-to-Back (FB2B): Hardwired to 0. Reserved
RO 0b RO 1b RO 0b
66/60MHz capability (CAP66): Hardwired to 0. Capabilities List: This bit indicates that a capabilities list is present. Hardwired to 1. INTA Status: This field indicates that an interrupt message is pending internally to the device. Only PME and Hot Plug sources feed into this status bit (not PCI INTA-INTD assert and de-assert messages). The INTA Assertion Disable bit, PCICMD1[10], has no effect on this bit. Reserved
2:0
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8.1.5
RID1--Revision Identification (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 08h 00h RO 8 bits
This register contains the revision number of the MCH device 1.
Bit 7:0 Access & Default RO 00h Description Revision Identification Number (RID1): This field indicates the number of times that this device in this component has been "stepped" through the manufacturing process. It is always the same as the RID values in all other devices in this component. 05h = B-2 Stepping
8.1.6
CC1--Class Code (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 09h 060400h RO 24 bits
This register identifies the basic function of the device, a more specific sub-class, and a registerspecific programming interface.
Bit 23:16 Access & Default RO 06h Description Base Class Code (BCC): This field indicates the base class code for this device. 06h = Bridge device. 15:8 RO 04h Sub-Class Code (SUBCC): This field indicates the sub-class code for this device. 04h = PCI-to-PCI Bridge. 7:0 RO 00h Programming Interface (PI): This field indicates the programming interface of this device. This value does not specify a particular register set layout and provides no practical use for this device.
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8.1.7
CL1--Cache Line Size (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 0Ch 00h R/W 8 bits
Bit 7:0
Access & Default R/W 00h
Description Cache Line Size (Scratch pad): This field is implemented by PCI Express* devices as a read/write field for legacy compatibility purposes but has no impact on any PCI Express device functionality.
8.1.8
HDR1--Header Type (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 0Eh 01h RO 8 bits
This register identifies the header layout of the configuration space. No physical register exists at this location.
Bit 7:0 Access & Default RO 01h Description Header Type Register (HDR): This field returns 01h to indicate that this is a single function device with bridge header layout.
8.1.9
PBUSN1--Primary Bus Number (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 18h 00h RO 8 bits
This register identifies that this "virtual" Host-PCI Express bridge is connected to PCI bus 0.
Bit 7:0 Access & Default RO 00h Description Primary Bus Number (BUSN): Configuration software typically programs this field with the number of the bus on the primary side of the bridge. Since device 1 is an internal device and its primary bus is always 0, these bits are read only and are hardwired to 0.
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8.1.10
SBUSN1--Secondary Bus Number (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 19h 00h RO 8 bits
This register identifies the bus number assigned to the second bus side of the "virtual" bridge i.e. to PCI Express Graphics. This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI Express Graphics.
Bit 7:0 Access & Default R/W 00h Description Secondary Bus Number (BUSN): This field is programmed by configuration software with the bus number assigned to PCI Express*-G.
8.1.11
SUBUSN1--Subordinate Bus Number (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 1Ah 00h R/W 8 bits
This register identifies the subordinate bus (if any) that resides at the level below PCI Express Graphics. This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI Express Graphics.
Bit 7:0 Access & Default R/W 00h Description Subordinate Bus Number (BUSN): This register is programmed by configuration software with the number of the highest subordinate bus that lies behind the device 1 bridge. When only a single PCI device resides on the PCI Express*-G segment, this register will contain the same value as the SBUSN1 register.
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8.1.12
IOBASE1--I/O Base Address (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 1Ch F0h RO 8 bits
This register controls the processor-to-PCI Express Graphics I/O access routing based on the following formula: IO_BASE address IO_LIMIT Only the upper 4 bits are programmable. For the purpose of address decode, address bits A[11:0] are treated as 0. Thus, the bottom of the defined I/O address range will be aligned to a 4-KB boundary.
Bit 7:4 Access & Default R/W Fh Description I/O Address Base (IOBASE): This field corresponds to A[15:12] of the I/O addresses passed by bridge 1 to PCI Express*-G. BIOS must not set this register to 00h; otherwise, 0CF8h/0CFCh accesses will be forwarded to the PCI Express hierarchy associated with this device. Reserved
3:0
8.1.13
IOLIMIT1--I/O Limit Address (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 1Dh 00h R/W 8 bits
This register controls the processor-to-PCI Express Graphics I/O access routing based on the following formula: IO_BASE address IO_LIMIT Only the upper 4 bits are programmable. For the purposes of address decode, address bits A[11:0] are assumed to be FFFh. Thus, the top of the defined I/O address range will be at the top of a 4KB aligned address block.
Bit 7:4 Access & Default R/W 0h Description I/O Address Limit (IOLIMIT): This field corresponds to A[15:12] of the I/O address limit of device 1. Devices between this upper limit and IOBASE1 will be passed to the PCI Express* hierarchy associated with this device. Reserved
3:0
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8.1.14
SSTS1--Secondary Status (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 1Eh 00h RO, R/W/C 16 bits
SSTS1 is a 16-bit status register that reports the occurrence of error conditions associated with secondary side (i.e., PCI Express Graphics side) of the "virtual" PCI-PCI Bridge in the MCH.
Bit 15 Access & Default R/WC 0b Detected Parity Error (DPE): 1 = The MCH received across the link (upstream) a Posted Write Data Poisoned TLP (EP=1). Received System Error (RSE): 1 = Secondary side sends an ERR_FATAL or ERR_NONFATAL message due to an error detected by the secondary side, and the SERR Enable bit in the Bridge Control register is 1. Received Master Abort (RMA): 1 = Secondary Side for Type 1 Configuration Space Header Device (for requests initiated by the Type 1 Header Device itself) receives a completion with Unsupported Request Completion Status. Received Target Abort (RTA): 1 = Secondary Side for Type 1 Configuration Space Header Device (for requests initiated by the Type 1 Header Device itself) receives a completion with Completer Abort Completion Status. Signaled Target Abort (STA): Hardwired to 0. The MCH does not generate Target Aborts (the MCH will never complete a request using the Completer Abort Completion status). DEVSELB Timing (DEVT): Hardwired to 0. Master Data Parity Error (SMDPE): 1 = The MCH received across the link (upstream) a Read Data Completion Poisoned TLP (EP=1). Note: This bit can only be set when the Parity Error Enable bit in the Bridge Control register is set. 7 6 5 4:0 RO 0b RO 0b Fast Back-to-Back (FB2B): Hardwired to 0. Reserved 66/60 MHz capability (CAP66): Hardwired to 0. Reserved Description
14
R/WC 0b
13
R/WC 0b
12
R/WC 0b
11
RO 0b RO 00b R/WC 0b
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8.1.15
MBASE1--Memory Base Address (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 20h FFF0h R/W 16 bits
This register controls the processor to PCI Express Graphics non-prefetchable memory access routing based on the following formula: MEMORY_BASE address MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32-bit address. The bottom 4 bits of this register are read-only and return zeroes when read. The configuration software must initialize this register. For the purpose of address decode, address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory address range will be aligned to a 1-MB boundary.
Bit 15:4 3:0 Access & Default R/W FFFh Description Memory Address Base (MBASE): This field corresponds to A[31:20] of the lower limit of the memory range that will be passed to PCI Express*. Reserved
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8.1.16
MLIMIT1--Memory Limit Address (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 22h 0000h R/W 16 bits
This register controls the processor-to-PCI Express Graphics non-prefetchable memory access routing based on the following formula: MEMORY_BASE address MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32-bit address. The bottom 4 bits of this register are read-only and return zeroes when read. Configuration software must initialize this register. For the purpose of address decode, address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory address range will be at the top of a 1-MB aligned memory block. Note: Memory range covered by MBASE and MLIMIT registers are used to map non-pre-fetchable PCI Express Graphics address ranges (typically, where control/status memory-mapped I/O data structures of the graphics controller will reside) and PMBASE and PMLIMIT are used to map prefetchable address ranges (typically, graphics local memory). This segregation allows application of USWC space attribute to be performed in a true plug-and-play manner to the pre-fetchable address range for improved processor-PCI Express memory access performance. Note: Configuration software is responsible for programming all address range registers (pre-fetchable, non-prefetchable) with the values that provide exclusive address ranges (i.e., prevent overlap with each other and/or with the ranges covered with the main memory). There is no provision in the MCH hardware to enforce prevention of overlap and operations of the system in the case of overlap are not guaranteed.
Bit 15:4 3:0 Access & Default R/W 000h Description Memory Address Limit (MLIMIT): This field corresponds to A[31:20] of the upper limit of the address range passed to PCI Express*. Reserved
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8.1.17
PMBASE1--Prefetchable Memory Base Address (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 24h FFF0h RO, R/W 16 bits
This register, in conjunction with the corresponding Upper Base Address register, controls the processor-to-PCI Express Graphics prefetchable memory access routing based on the following formula: PREFETCHABLE_MEMORY_BASE address PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read/write and correspond to address bits A[31:20] of the 40bit address. The lower 8 bits of the Upper Base Address register are read/write and correspond to address bits A[39:32] of the 40-bit address. The configuration software must initialize this register. For the purpose of address decode, address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory address range will be aligned to a 1-MB boundary.
Bit 15:4 Access & Default R/W FFFh RO 0h Description Prefetchable Memory Base Address (MBASE): This field corresponds to A[31:20] of the lower limit of the memory range that will be passed to PCI Express*. 64-bit Address Support: This field indicates that the bridge supports only 32 bit addresses.
3:0
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8.1.18
PMLIMIT1--Prefetchable Memory Limit Address (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 26h 0000h RO, R/W 16 bits
This register, in conjunction with the corresponding Upper Limit Address register, controls the processor-to-PCI Express Graphics prefetchable memory access routing based on the following formula: PREFETCHABLE_MEMORY_BASE address PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read/write and correspond to address bits A[31:20] of the 40bit address. The lower 8 bits of the Upper Limit Address register are read/write and correspond to address bits A[39:32] of the 40-bit address. The configuration software must initialize this register. For the purpose of address decode, address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory address range will be at the top of a 1-MB aligned memory block. Note that prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that must be defined as UC and the ones that can be designated as a USWC (i.e., prefetchable) from the processor perspective.
Bit 15:4 3:0
Access & Default R/W 000h RO 0h
Description Prefetchable Memory Address Limit (PMLIMIT): This field corresponds to A[31:20] of the upper limit of the address range passed to PCI Express*. 64-bit Address Support: This field indicates the bridge supports only 32 bit addresses.
8.1.19
CAPPTR1--Capabilities Pointer (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 34h 88h RO 8 bits
The capabilities pointer provides the address offset to the location of the first entry in this device's linked list of capabilities.
Bit 7:0 Access & Default RO 88h Description First Capability (CAPPTR1): The first capability in the list is the Subsystem ID and Subsystem Vendor ID Capability.
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8.1.20
INTRLINE1--Interrupt Line (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 3Ch 00h R/W 8 bits
This register contains interrupt line routing information. The device itself does not use this value; rather device drivers and operating systems use it to determine priority and vector information.
Bit 7:0 Access & Default R/W 00h Description Interrupt Connection: This field is used to communicate interrupt line routing information. POST software writes the routing information into this register as it initializes and configures the system. The value in this register indicates which input of the system interrupt controller this device's interrupt pin is connected to.
8.1.21
INTRPIN1--Interrupt Pin (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 3Dh 00h RO 8 bits
This register specifies which interrupt pin this device uses.
Bit 7:0 Access & Default RO 01h Description Interrupt Pin: As a single function device, the PCI Express* device specifies INTA as its interrupt pin. 01h = INTA
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8.1.22
BCTRL1--Bridge Control (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 3Eh 0000h RO, R/W 16 bits
This register provides extensions to the PCICMD1 register that are specific to PCI-PCI bridges. The BCTRL provides additional control for the secondary interface (i.e., PCI Express) as well as some bits that affect the overall behavior of the "virtual" Host-PCI Express bridge embedded within MCH (e.g., VGA compatible address ranges mapping).
Bit 15:12 11 10 9 8 7 6 5 RO 0b RO 0b RO 0b RO 0b RO 0b R/W 0b RO 0b R/W 0b Access & Default Reserved Discard Timer SERR Enable: Hardwired to 0. Discard Timer Status: Hardwired to 0. Secondary Discard Timer: Hardwired to 0. Primary Discard Timer: Hardwired to 0. Fast Back-to-Back Enable (FB2BEN): Hardwired to 0. Secondary Bus Reset (SRESET): Setting this bit triggers a hot reset on the corresponding PCI Express* Port. Master Abort Mode (MAMODE): When acting as a master, unclaimed reads that experience a master abort returns all 1s and any writes that experience a master abort completes normally and the data is thrown away. Hardwired to 0. VGA 16-bit Decode: This bit enables the PCI-to-PCI bridge to provide 16-bit decoding of VGA I/O address precluding the decoding of alias addresses every 1 KB. This bit only has meaning if bit 3 (VGA Enable) of this register is also set to 1, enabling VGA I/O decoding and forwarding by the bridge. 0 = Execute 10-bit address decodes on VGA I/O accesses. 1 = Execute 16-bit address decodes on VGA I/O accesses. 3 R/W 0b VGA Enable (VGAEN): This bit controls the routing of processor-initiated transactions targeting VGA compatible I/O and memory address ranges. See the VGAEN/MDAP table in Device 0, offset 97h[0]. Description
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Bit 2
Access & Default R/W 0b
Description ISA Enable (ISAEN): This bit is needed to exclude legacy resource decode to route ISA resources to legacy decode path. This bit modifies the response by the MCH to an I/O access issued by the processor that target ISA I/O addresses. This applies only to I/O addresses that are enabled by the IOBASE and IOLIMIT registers. 0 = All addresses defined by the IOBASE and IOLIMIT for processor I/O transactions will be mapped to PCI Express Graphics. 1 = MCH will not forward to PCI Express Graphics any I/O transactions addressing the last 768 bytes in each 1-KB block, even if the addresses are within the range defined by the IOBASE and IOLIMIT registers. Instead of going to PCI Express Graphics, these cycles are forwarded to DMI where they can be subtractively or positively claimed by the ISA bridge.
1
R/W 0b
SERR Enable (SERREN) 0 = No forwarding of error messages from secondary side to primary side that could result in an SERR. 1 = ERR_COR, ERR_NONFATAL, and ERR_FATAL messages result in SERR message when individually enabled by the Root Control register.
0
RO 0b
Parity Error Response Enable (PEREN): This bit controls whether or not the Master Data Parity Error bit in the Secondary Status register is set when the MCH receives across the link (upstream) a Read Data Completion Poisoned TLP. 0 = Master Data Parity Error bit in Secondary Status register cannot be set. 1 = Master Data Parity Error bit in Secondary Status register can be set..
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8.1.23
PM_CAPID1--Power Management Capabilities (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 80h 1902 9001h or 1902 A001h RO 32 bits
Bit 31:27
Access & Default RO 19h
Description PME Support: This field indicates the power states in which this device may indicate PME wake via PCI Express messaging. D0, D3hot, and D3cold. This device is not required to do anything to support D3hot and D3cold; it simply must report that those states are supported. Refer to the PCI Power Management 1.1 specification for encoding explanation and other power management details. D2: Hardwired to 0 to indicate that the D2 power management state is NOT supported. D1: Hardwired to 0 to indicate that the D1 power management state is NOT supported. Auxiliary Current: Hardwired to 0 to indicate that there are no 3.3Vaux auxiliary current requirements. Device Specific Initialization (DSI): Hardwired to 0 to indicate that special initialization of this device is NOT required before generic class device driver is to use it. Auxiliary Power Source (APS): Hardwired to 0. PME Clock: Hardwired to 0 to indicate this device does NOT support PME# generation. PCI PM CAP Version: Hardwired to 02h to indicate there are 4 bytes of power management registers implemented and that this device complies with revision 1.1 of the PCI Power Management Interface Specification. Pointer to Next Capability: This field contains a pointer to the next item in the capabilities list. If MSICH (CAPL[0] @ 7Fh) is 0, then the next item in the capabilities list is the Message Signaled Interrupts (MSI) capability at 90h. If MSICH (CAPL[0] @ 7Fh) is 1, then the next item in the capabilities list is the PCI Express* capability at A0h. Capability ID: Value of 01h identifies this linked list item (capability structure) as being for PCI Power Management registers.
26 25 24:22 21
RO 0b RO 0b RO 000b RO 0b RO 0b RO 0b RO 010b RO 90h or A0h RO 01h
20 19 18:16
15:8
7:0
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PM_CS1--Power Management Control/Status (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 84h 00000000h RO, R/W/S 32 bits
Bit 31:16 15 14:13 12:9 8
Access & Default Reserved RO 0b RO 00b RO 0h R/W/S 0b
Description
PME Status: This bit indicates that this device does not support PME# generation from D3cold. Data Scale: This field indicates that this device does not support the power management data register. Data Select: This field indicates that this device does not support the power management data register. PME Enable: This bit indicates that this device does not generate PMEB assertion from any D-state. 0 = PMEB generation not possible from any D State 1 = PMEB generation enabled from any D State The setting of this bit has no effect on hardware. See PM_CAP[15:11]
7:2 1:0 R/W 00b
Reserved Power State: This field indicates the current power state of this device and can be used to set the device into a new power state. If software attempts to write an unsupported state to this field, write operation must complete normally on the bus, but the data is discarded and no state change occurs. 00 = D0 01 = D1 (Not supported in this device.) 10 = D2 (Not supported in this device.) 11 = D3 Support of D3cold does not require any special action. While in the D3hot state, this device can only act as the target of PCI configuration transactions (for power management control). This device also cannot generate interrupts or respond to MMR cycles in the D3 state. The device must return to the D0 state to be fully functional. There is no hardware functionality required to support these power states.
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Host-PCI Express* Graphics Bridge Registers (D1:F0)
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8.1.25
SS_CAPID--Subsystem ID and Vendor ID Capabilities (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 88h 0000800Dh RO 32 bits
This capability is used to uniquely identify the subsystem where the PCI device resides. Because this device is an integrated part of the system and not an add-in device, it is anticipated that this capability will never be used. However, it is necessary because Microsoft will test for its presence.
Bit 31:16 15:8 7:0
Access & Default Reserved RO 80h RO 0D h
Description
Pointer to Next Capability: This field contains a pointer to the next item in the capabilities list which is the PCI Power Management capability. Capability ID: A value of 0Dh identifies this linked list item (capability structure) as being for SSID/SSVID registers in a PCI-to-PCI Bridge.
8.1.26
SS--Subsystem ID and Subsystem Vendor ID (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 8Ch 00008086h RO 32 bits
System BIOS can be used as the mechanism for loading the SSID/SVID values. These values must be preserved through power management transitions and hardware reset.
Bit 31:16 15:0 Access & Default R/WO 0000h R/WO 8086h Description Subsystem ID (SSID): This field identifies the particular subsystem and is assigned by the vendor. Subsystem Vendor ID (SSVID): This field identifies the manufacturer of the subsystem and is the same as the vendor ID that is assigned by the PCI Special Interest Group.
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8.1.27
MSI_CAPID--Message Signaled Interrupts Capability ID (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 90h A005h RO 16 bits
When a device supports MSI, it can generate an interrupt request to the processor by writing a predefined data item (a message) to a predefined memory address. The reporting of the existence of this capability can be disabled by setting MSICH (CAPL [0] @ 7Fh). In that case walking this linked list will skip this capability and, instead, go directly from the PCI PM capability to the PCI Express capability.
Bit 15:8 7:0
Access & Default RO A0h RO 05h
Description Pointer to Next Capability: This field contains a pointer to the next item in the capabilities list that is the PCI Express* capability. Capability ID: 05h = Identifies this linked list item (capability structure) as being for MSI registers.
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8.1.28
MC--Message Control (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 92h 0000h RO, R/W 16 bits
System software can modify bits in this register, but the device is prohibited from doing so. If the device writes the same message multiple times, only one of those messages is guaranteed to be serviced. If all of them must be serviced, the device must not generate the same message again until the driver services the earlier one.
Bit 15:8 7
Access & Default Reserved RO 0b R/W 000b
Description
64-bit Address Capable: Hardwired to 0 to indicate that the function does not implement the upper 32 bits of the Message Address register and is incapable of generating a 64-bit memory address. Multiple Message Enable (MME): System software programs this field to indicate the actual number of messages allocated to this device. This number will be equal to or less than the number actually requested. 000 = 1 message allocated 001-111 = Reserved
6:4
3:1
RO 000b
Multiple Message Capable (MMC): System software reads this field to determine the number of messages being requested by this device. 000 = 1 message requested 001-111 = Reserved
0
R/W 0b
MSI Enable (MSIEN) Controls the ability of this device to generate MSIs. 0 = MSI will not be generated. 1 = MSI will be generated when we receive PME or HotPlug messages. INTA will not be generated and INTA Status (PCISTS1[3]) will not be set.
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8.1.29
MA--Message Address (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 94h 00000000h RO, R/W 32 bits
Bit 31:2
Access & Default R/W 00000000 h
Description Message Address: This field is used by system software to assign an MSI address to the device. The device handles an MSI by writing the padded contents of the MD register to this address.
1:0
RO 00b
Force DWord Align: Hardwired to 0 so that addresses assigned by system software are always aligned on a DWord address boundary.
8.1.30
MD--Message Data (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 98h 0000h R/W 16 bits
Bit 15:0
Access & Default R/W 0000h
Description Message Data: This field provides a base message data pattern assigned by system software and used to handle an MSI from the device. When the device must generate an interrupt request, it writes a 32-bit value to the memory address specified in the MA register. The upper 16 bits are always set to 0. This register supplies the lower 16 bits.
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8.1.31
PEG_CAPL--PCI Express* Capability List (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 A0h 0010h RO 16 bits
This register enumerates the PCI Express capability structure.
Bit 15:8 Access & Default RO 00h Description Pointer to Next Capability: This value terminates the capabilities list. The Virtual Channel capability and any other PCI Express* specific capabilities that are reported via this mechanism are in a separate capabilities list located entirely within PCI Express extended configuration space. Capability ID: This field identifies this linked list item (capability structure) as being for PCI Express registers.
7:0
RO 10h
8.1.32
PEG_CAP--PCI Express*-G Capabilities (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 A2h 0141h RO 16 bits
Indicates PCI Express device capabilities.
Bit 15:14 13:9 8 RO 00h R/WO 1b Access & Default Reserved Interrupt Message Number: Hardwired to 0. Slot Implemented 0 = The PCI Express* Link associated with this port is connected to an integrated component or is disabled. 1 = The PCI Express Link associated with this port is connected to a slot. BIOS must initialize this field appropriately if a slot connection is not implemented. 7:4 3:0 RO 4h RO 1h Device/Port Type: Hardwired to 0100 to indicate root port of PCI Express Root Complex. PCI Express Capability Version: Hardwired to 1 as it is the first version. Description
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8.1.33
DCAP--Device Capabilities (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 A4h 00000000h RO 32 bits
This register indicates PCI Express link capabilities.
Bit 31:6 5 4:3 2:0 RO 0b RO 00b RO 000b Access & Default Reserved Extended Tag Field Supported: Hardwired to indicate support for 5-bit Tags as a Requestor. Phantom Functions Supported: Hardwired to 0. Max Payload Size: Hardwired to indicate 128B maximum supported payload for Transaction Layer Packets (TLP). Description
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8.1.34
DCTL--Device Control (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 A8h 0000h R/W 16 bits
This register provides control for PCI Express device specific capabilities. The error reporting enable bits are in reference to errors detected by this device, not error messages received across the link. The reporting of error messages (ERR_CORR, ERR_NONFATAL, ERR_FATAL) received by Root Port is controlled exclusively by Root Port Command Register.
Bit 15:8 7:5 R/W 000b Access & Default Reserved Max Payload Size 000 = 128B maximum supported payload for Transaction Layer Packets (TLP). As a receiver, the device must handle TLPs as large as the set value; as transmitter, the device must not generate TLPs exceeding the set value. Note: All other encodings are reserved. 4 3 R/W 0b Reserved Unsupported Request Reporting Enable: 0 = Disable. 1 = Enable. Unsupported Requests will be reported. Note that reporting of error messages received by Root Port is controlled exclusively by Root Control register. 2 R/W 0b Fatal Error Reporting Enable: 0 = Disable. 1 = Enable. Fatal errors will be reported. For a Root Port, the reporting of fatal errors is internal to the root. No external ERR_FATAL message is generated. 1 R/W 0b Non-Fatal Error Reporting Enable: 0 = Disable. 1 = Enable. Non-fatal errors will be reported. For a Root Port, the reporting of non-fatal errors is internal to the root. No external ERR_NONFATAL message is generated. Uncorrectable errors can result in degraded performance. 0 R/W 0b Correctable Error Reporting Enable: 0 = Disable. 1 = Enable. Correctable errors will be reported. For a Root Port, the reporting of correctable errors is internal to the root. No external ERR_CORR message is generated. Description
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8.1.35
DSTS--Device Status (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 AAh 0000h RO 16 bits
This register reflects status corresponding to controls in the Device Control register. Note: The error reporting bits are in reference to errors detected by this device, not errors messages received across the link.
Bit 15:6 5
Access & Default Reserved RO 0b Transactions Pending
Description
0 = All pending transactions (including completions for any outstanding nonposted requests on any used virtual channel) have been completed. 1 = Device has transaction(s) pending (including completions for any outstanding non-posted requests for all used Traffic Classes).
4 3 R/WC 0b
Reserved Unsupported Request Detected: 1 = Device received an Unsupported Request. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control Register. Fatal Error Detected: 1 = Fatal error(s) were detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. Non-Fatal Error Detected: 1 = Non-fatal error(s) were detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. Correctable Error Detected: 1 = Correctable error(s) were detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. Note: The MCH may report a false 8B/10B Receiver Error when exiting L0s. This is reported thru the Correctable Error Detected bit CESTS device 1, offset 1D0h, Bit [0]. This will reduce the value of Receiver Error detection when L0s is enabled. Disable L0s for accurate Receiver Error reporting.
2
R/WC 0b
1
R/WC 0b
0
R/WC 0b
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8.1.36
LCAP--Link Capabilities (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 ACh 02012E01h R/WO 16 bits
This register indicates PCI Express device specific capabilities.
Bit 31:24 Access & Default RO 02h Description Port Number: This field indicates the PCI Express* port number for the given PCI Express link. This field matches the value in Element Self Description [31:24]. Reserved R/WO 010b L1 Exit Latency: This field indicates the length of time this Port requires to complete the transition from L1 to L0. The value 010 b indicates the range of 2 s to less than 4 s. If this field is required to be any value other than the default, BIOS must initialize it accordingly. Both bytes of this register that contain a portion of this field must be written simultaneously in order to prevent an intermediate (and undesired) value from ever existing. 14:12 R/WO 010b L0s Exit Latency: This field indicates the length of time this Port requires to complete the transition from L0s to L0. The value 010 b indicates the range of 128 ns to less than 256 ns. If this field is required to be any value other than the default, BIOS must initialize it accordingly. Note: When PCI Express* is operating with separate reference clocks, L0s exit latency may be greater than the setting in the L0s Exit Latency Register. Expect longer exit latency then setting in L0s Exit Latency Register. The link may enter Recovery state before reaching L0. System BIOS can program the appropriate Exit Latency and advertised N_FTS value if it detects that the downstream device is not using the common reference clock (indicated in the Slot Clock Configuration bit 12 of the device's Link Status Register) 11:10 9:4 R/WO 11b RO 10h Active State Link PM Support: L0s and L1 entry supported. Max Link Width: Hardwired to indicate X16. When Force X1 mode is enabled on this PCI Express* x16 Graphics Interface device, this field reflects X1 (01h). Max Link Speed: Hardwired to indicate 2.5 Gb/s.
23:18 17:15
3:0
RO 1h
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8.1.37
LCTL--Link Control (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 B0h 0000h RO, R/W 16 bits
This register allows control of PCI Express link.
Bit 15:8 7 6 R/W 0b Access & Default Reserved Reserved. Must be 0 when writing this register. Common Clock Configuration 0 = This component and the component at the opposite end of this Link are operating with asynchronous reference clock. 1 = This component and the component at the opposite end of this Link are operating with a distributed common reference clock. Components use this common clock configuration information to report the correct L0s and L1 Exit Latencies. 5 R/W 0b Retrain Link 0 = Normal operation 1 = Full Link retraining is initiated by directing the Physical Layer LTSSM from L0, L0s, or L1 states to the Recovery state. This bit always returns 0 when read. This bit is cleared automatically (no need to write a 0). 4 R/W 0b Link Disable 0 = Normal operation 1 = Link is disabled. Forces the LTSSM to transition to the Disabled state (via Recovery) from L0, L0s, or L1 states. Link retraining happens automatically on 0 to 0 transition, just like when coming out of reset. Writes to this bit are immediately reflected in the value read from the bit, regardless of actual Link state. 3 2 1:0 R/W 00b RO 0b Read Completion Boundary (RCB): Hardwired to 0 to indicate 64 byte. Reserved Active State PM: This field controls the level of active state power management supported on the given link. 00 = Disabled 01 = L0s Entry Supported 10 = Reserved 11 = L0s and L1 Entry Supported Description
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8.1.38
LSTS--Link Status (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 B2h 1001h RO 16 bits
This register indicates PCI Express link status.
Bit 15:13 12 RO 1b Access & Default Reserved Slot Clock Configuration 0 = The device uses an independent clock irrespective of the presence of a reference on the connector. 1 = The device uses the same physical reference clock that the platform provides on the connector. 11 RO 0b Link Training: 1 = Link training is in progress. Hardware clears this bit once Link training is complete. Training Error: 1 = This bit is set by hardware upon detection of unsuccessful training of the Link to the L0 Link state. Negotiated Width: This field indicates negotiated link width. This field is valid only when the link is in the L0, L0s, or L1 states (after link width negotiation is successfully completed). 00h = Reserved 01h = X1 04h = Reserved 08h = Reserved 10h = X16 All other encodings are reserved. 3:0 RO 1h Negotiated Speed: This field indicates negotiated link speed. 1h = 2.5 Gb/s All other encodings are reserved. Description
10
RO 0b
9:4
RO 00h
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8.1.39
SLOTCAP--Slot Capabilities (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 B4h 00000000h R/WO 32 bits
PCI Express slot-related registers allow for the support of Hot-Plug.
Bit 31:19 Access & Default R/WO 0000h Description Physical Slot Number: This field indicates the physical slot number attached to this Port. This field must be initialized by BIOS to a value that assigns a slot number that is globally unique within the chassis. 18:17 Reserved
16:15
R/WO 00b
Slot Power Limit Scale: This field specifies the scale used for the Slot Power Limit Value. 00 = 1.0x 01 = 0.1x 10 = 0.01x 11 = 0.001x If this field is written, the link sends a Set_Slot_Power_Limit message.
14:7
R/WO 00h
Slot Power Limit Value: In combination with the Slot Power Limit Scale value, this field specifies the upper limit on power supplied by slot. Power limit (in Watts) is calculated by multiplying the value in this field by the value in the Slot Power Limit Scale field. If this field is written, the link sends a Set_Slot_Power_Limit message.
6 5 4 3 2:1 0
R/WO 0b R/WO 0b R/WO 0b R/WO 0b
Hot-plug Capable: This field indicates that this slot is capable of supporting Hot-plug operations. Hot-plug Surprise: This field indicates that a device present in this slot might be removed from the system without any prior notification. Power Indicator Present: This field indicates that a Power Indicator is implemented on the chassis for this slot. Attention Indicator Present: This field indicates that an Attention Indicator is implemented on the chassis for this slot. Reserved
R/WO 0b
Attention Button Present: This field indicates that an Attention Button is implemented on the chassis for this slot. The Attention Button allows the user to request hot-plug operations.
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SLOTCTL--Slot Control (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 B8h 01C0h R/W 16 bits
PCI Express slot related registers allow for the support of Hot-Plug.
Bit 15:10 9:8 R/W 01b Access & Default Reserved Power Indicator Control: Reads to this register return the current state of the Power Indicator. Writes to this register set the Power Indicator and cause the Port to send the appropriate POWER_INDICATOR_* messages. 00 = Reserved 01 = On 10 = Blink 11 = Off 7:6 R/W 11b Attention Indicator Control: Reads to this register return the current state of the Attention Indicator. Writes to this register set the Attention Indicator and cause the Port to send the appropriate ATTENTION_INDICATOR_* messages. 00 = Reserved 01 = On 10 = Blink 11 = Off 5 R/W 0b Hot plug Interrupt Enable: 0 = Disable. 1 = Enables generation of hot plug interrupt on enabled hot plug events. 4 R/W 0b Command Completed Interrupt Enable: 0 = Disable. 1 = Enables the generation of hot plug interrupt when the Hot plug controller completes a command. 3 R/W 0b Presence Detect Changed Enable: 0 = Disable. 1 = Enables the generation of hot plug interrupt or wake message on a presence detect changed event. 2:1 0 R/W 0b Reserved Attention Button Pressed Enable: 0 = Disable. 1 = Enables the generation of hot plug interrupt or wake message on an attention button pressed event. Description
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SLOTSTS--Slot Status (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 BAh 0X00h RO, R/W/C 16 bits
PCI Express slot-related registers allow for the support of Hot-Plug.
Bit 15:7 6 RO Xb Access & Default Reserved Presence Detect State: This bit indicates the presence of a card in the slot. 0 = Slot Empty 1 = Card Present in slot. Reserved R/WC 0b R/WC 0b Command Completed: 1 = Hot plug controller completed an issued command. Presence Detect Changed: 1 = Presence Detect change is detected. This corresponds to an edge on the signal that corresponds to bit 6 of this register (Presence Detect State). Reserved R/WC 0b Attention Button Pressed: 1 = Attention Button is pressed. Description
5 4
3
2:1 0
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8.1.42
RCTL--Root Control (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 BCh 0000h R/W 16 bits
This register allows control of PCI Express Root Complex specific parameters. The system error control bits in this register determine if corresponding SERRs are generated when our device detects an error (reported in this device's Device Status register) or when an error message is received across the link. Reporting of SERR as controlled by these bits takes precedence over the SERR Enable in the PCI Command Register.
Bit 15:4 3
Access & Default Reserved R/W 0b PME Interrupt Enable
Description
0 = No interrupts are generated as a result of receiving PME messages. 1 = Enables interrupt generation upon receipt of a PME message as reflected in the PME Status bit of the Root Status Register. A PME interrupt is also generated if the PME Status bit of the Root Status Register is set when this bit is set from a cleared state.
2
R/W 0b
System Error on Fatal Error Enable: This bit controls the Root Complex's response to fatal errors. 0 = No SERR generated on receipt of fatal error. 1 = Indicates that an SERR should be generated if a fatal error is reported by any of the devices in the hierarchy associated with this Root Port, or by the Root Port itself.
1
R/W 0b
System Error on Non-Fatal Uncorrectable Error Enable: This bit controls the Root Complex's response to non-fatal errors. 0 = No SERR generated on receipt of non-fatal error. 1 = Indicates that an SERR should be generated if a non-fatal error is reported by any of the devices in the hierarchy associated with this Root Port, or by the Root Port itself.
0
R/W 0b
System Error on Correctable Error Enable: This bit controls the Root Complex's response to correctable errors. 0 = No SERR generated on receipt of correctable error. 1 = Indicates that an SERR should be generated if a correctable error is reported by any of the devices in the hierarchy associated with this Root Port, or by the Root Port itself.
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RSTS--Root Status (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 C0h 00000000h RO, R/W/C 32 bits
This register provides information about PCI Express Root Complex specific parameters.
Bit 31:18 17 RO 0b Access & Default Reserved PME Pending: This bit indicates that another PME is pending when the PME Status bit is set. When the PME Status bit is cleared by software; the PME is delivered by hardware by setting the PME Status bit again and updating the Requestor ID appropriately. The PME pending bit is cleared by hardware if no more PMEs are pending. PME Status: This bit indicates that the requestor ID indicated in the PME Requestor ID field asserted PME. Subsequent PMEs are kept pending until the status register is cleared by writing a 1 to this field. PME Requestor ID: This field indicates the PCI requestor ID of the last PME requestor. Description
16
R/W/C 0b RO 0000h
15:0
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PEGLC--PCI Express*-G Legacy Control
PCI Device: Address Offset: Default Value: Access: Size: 1 ECh 00000000h RO, R/W 32 bits
This register controls functionality that is needed by Legacy (non-PCI Express aware) OS's during run time.
Bit 31:3 Access & Default RO 0000 0000h R/W 0b Reserved Description
2
PME GPE Enable (PMEGPE): 0 = Do not generate GPE PME message when PME is received. 1 = Enable. Generate a GPE PME message when PME is received (Assert_PMEGPE and Deassert_PMEGPE messages on DMI). This enables the MCH to support PMEs on the PCI Express* x16 Graphics Interface port under legacy OSs.
1
R/W 0b
Hot-Plug GPE Enable (HPGPE) 0 = Do not generate GPE Hot-Plug message when Hot-Plug event is received. 1 = Enable. Generate a GPE Hot-Plug message when Hot-Plug Event is received (Assert_HPGPE and Deassert_HPGPE messages on DMI). This enables the MCH to support Hot-Plug on the PCI Express* x16 Graphics Interface port under legacy OSs.
0
R/W 0b
General Message GPE Enable (GENGPE) 0 = Do not forward received GPE assert/deassert messages. 1 = Enable. Forward received GPE assert/deassert messages. These general GPE message can be received via the PCI Express* x16 Graphics Interface port from an external Intel device and will be subsequently forwarded to the Intel(R) ICH6 (via Assert_GPE and Deassert_GPE messages on DMI).
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VCECH--Virtual Channel Enhanced Capability Header (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 100h 14010002h RO 32 bits
This register indicates PCI Express device Virtual Channel capabilities. Note: Extended capability structures for PCI Express devices are located in PCI Express extended configuration space and have different field definitions than standard PCI capability structures.
Bit 31:20 19:16 15:0 Access & Default RO 140h RO 1h RO 0002h Description Pointer to Next Capability: The Link Declaration Capability is the next in the PCI Express* extended capabilities list. PCI Express Virtual Channel Capability Version: Hardwired to 1 to indicate compliances with the 1.0a version of the PCI Express specification. Extended Capability ID: Value of 0002 h identifies this linked list item (capability structure) as being for PCI Express Virtual Channel registers.
8.1.46
PVCCAP1--Port VC Capability Register 1 (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 104h 00000001h RO, R/WO 32 bits
This register describes the configuration of PCI Express Virtual Channels associated with this port.
Bit 31:7 6:4 RO 000b Access & Default Reserved Low Priority Extended VC Count: This field indicates the number of (extended) Virtual Channels in addition to the default VC belonging to the low-priority VC (LPVC) group that has the lowest priority with respect to other VC resources in a strict-priority VC Arbitration. The value of 0 in this field implies strict VC arbitration. 3 2:0 R/WO 001b Reserved Extended VC Count: This field indicates the number of (extended) Virtual Channels in addition to the default VC supported by the device. Description
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8.1.47
PVCCAP2--Port VC Capability Register 2 (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 108h 00000001h RO 32 bits
This register describes the configuration of PCI Express Virtual Channels associated with this port.
Bit 31:24 Access & Default RO 00h Description VC Arbitration Table Offset: This field indicates the location of the VC Arbitration Table. This field contains the zero-based offset of the table in DQWORDS (16 bytes) from the base address of the Virtual Channel Capability Structure. A value of 0 indicates that the table is not present (due to fixed VC priority). Reserved RO 01h VC Arbitration Capability: This field indicates that the only possible VC arbitration scheme is hardware fixed (in the root complex). VC1 is the highest priority, VC0 is the lowest priority.
23:8 7:0
8.1.48
PVCCTL--Port VC Control (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size:
Bit 15:4 3:1 R/W 000b Access & Default Reserved VC Arbitration Select: This field will be programmed by software to the only possible value as indicated in the VC Arbitration Capability field. The value 001b when written to this field will indicate the VC arbitration scheme is hardware fixed (in the root complex). This field can not be modified when more than one VC in the LPVC group is enabled. 0 Reserved
1 10Ch 0000h R/W 16 bits
Description
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VC0RCAP--VC0 Resource Capability (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 110h 00000000h RO 32 bits
Bit 31:16 15
Access & Default Reserved RO 0b Reject Snoop Transactions
Description
0 = Transactions with or without the No Snoop bit set within the TLP header are allowed on this VC. 1 = Any transaction without the No Snoop bit set within the TLP header will be rejected as an Unsupported Request.
14:0
Reserved
8.1.50
VC0RCTL--VC0 Resource Control (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 114h 8000007Fh RO, R/W 32 bits
This register controls the resources associated with PCI Express Virtual Channel 0.
Bit 31 30:27 26:24 23:8 7:1 R/W 7Fh RO 000b Access & Default RO 1b Description VC0 Enable: For VC0 this is hardwired to 1 and read only as VC0 can never be disabled. Reserved VC0 ID: This field assigns a VC ID to the VC resource. For VC0 this is hardwired to 0 and read only. Reserved TC/VC0 Map: This field indicates the TCs (Traffic Classes) that are mapped to the VC resource. Bit locations within this field correspond to TC values. For example, when bit 7 is set in this field, TC7 is mapped to this VC resource. When more than one bit in this field is set, it indicates that multiple TCs are mapped to the VC resource. In order to remove one or more TCs from the TC/VC Map of an enabled VC, software must ensure that no new or outstanding transactions with the TC labels are targeted at the given Link. TC0/VC0 Map: Traffic Class 0 is always routed to VC0.
0
RO 1b
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VC0RSTS--VC0 Resource Status (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 11Ah 0000h RO 16 bits
This register reports the Virtual Channel specific status.
Bit 15:2 1 RO 1b Access & Default Reserved VC0 Negotiation Pending 0 = The VC negotiation is complete. 1 = The VC resource is still in the process of negotiation (initialization or disabling). This bit indicates the status of the process of Flow Control initialization. It is set by default on Reset, as well as whenever the corresponding Virtual Channel is Disabled or the Link is in the DL_Down state. It is cleared when the link successfully exits the FC_INIT2 state Before using a Virtual Channel, software must check whether the VC Negotiation Pending fields for that Virtual Channel are cleared in both Components on a Link. 0 Reserved Description
8.1.52
VC1RCAP--VC1 Resource Capability (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 11Ch 00008000h RO 32 bits
Bit 31:16 15
Access & Default Reserved RO 1b Reject Snoop Transactions
Description
0 = Transactions with or without the No Snoop bit set within the TLP header are allowed on this VC. 1 = Any transaction without the No Snoop bit set within the TLP header will be rejected as an Unsupported Request.
14:0
Reserved
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8.1.53
VC1RCTL--VC1 Resource Control (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 120h 01000000h RO, R/W 32 bits
Controls the resources associated with PCI Express Virtual Channel 1.
Bit 31 Access & Default R/W 0b VC1 Enable 0 = Virtual Channel is disabled. 1 = Virtual Channel is enabled. See exceptions in note below. Software must use the VC Negotiation Pending bit to check whether the VC negotiation is complete. When VC Negotiation Pending bit is cleared, a 1 read from this VC Enable bit indicates that the VC is enabled (Flow Control Initialization is completed for the PCI Express* port); a 0 read from this bit indicates that the Virtual Channel is currently disabled. Notes: * To enable a Virtual Channel, the VC Enable bits for that Virtual Channel must be set in both Components on a Link. * To disable a Virtual Channel, the VC Enable bits for that Virtual Channel must be cleared in both Components on a Link. * Software must ensure that no traffic is using a Virtual Channel at the time it is disabled. * Software must fully disable a Virtual Channel in both Components on a Link before re-enabling the Virtual Channel. 30:27 26:24 R/W 001b Reserved VC1 ID: Assigns a VC ID to the VC resource. Assigned value must be non-zero. This field cannot be modified when the VC is already enabled. Reserved R/W 00h TC/VC1 Map: This field indicates the TCs (Traffic Classes) that are mapped to the VC resource. Bit locations within this field correspond to TC values. For example, when bit 7 is set in this field, TC7 is mapped to this VC resource. When more than one bit in this field is set, it indicates that multiple TCs are mapped to the VC resource. In order to remove one or more TCs from the TC/VC Map of an enabled VC, software must ensure that no new or outstanding transactions with the TC labels are targeted at the given Link. TC0/VC1 Map: Traffic Class 0 is always routed to VC0. Description
23:8 7:1
0
RO 0b
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8.1.54
VC1RSTS--VC1 Resource Status (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 126h 0000h RO 16 bits
This register reports the Virtual Channel specific status.
Bit 15:2 1 RO 1b Access & Default Reserved VC1 Negotiation Pending 0 = The VC negotiation is complete. 1 = The VC resource is still in the process of negotiation (initialization or disabling). This bit indicates the status of the process of Flow Control initialization. It is set by default on Reset, as well as when the corresponding Virtual Channel is Disabled or the Link is in the DL_Down state. It is cleared when the link successfully exits the FC_INIT2 state Before using a Virtual Channel, software must check whether the VC Negotiation Pending fields for that Virtual Channel are cleared in both Components on a Link. 0 Reserved Description
8.1.55
RCLDECH--Root Complex Link Declaration Enhanced Capability Header (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 140h 00010005h RO 32 bits
This capability declares links from this element (PCI Express* x16 Graphics Interface) to other elements of the root complex component to which it belongs. See the PCI Express specification for link/topology declaration requirements.
Bit 31:20 Access & Default RO 000h 19:16 15:0 RO 1h RO 0005h Description Pointer to Next Capability: This is the last capability in the PCI Express* extended capabilities list. Link Declaration Capability Version: Hardwired to 1 to indicate compliances with the 1.0a version of the PCI Express specification. Extended Capability ID: Value of 0005h identifies this linked list item (capability structure) as being for PCI Express Link Declaration Capability.
Note: See corresponding Egress Port Link Declaration Capability registers for diagram of Link Declaration Topology.
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ESD--Element Self Description (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 144h 02000100h RO, R/WO 32 bits
This register provides information about the root complex element containing this Link Declaration Capability.
Bit 31:24 Access & Default RO 02h Description Port Number: This field specifies the port number associated with this element with respect to the component that contains this element. The egress port of the component to provide arbitration to this Root Complex Element uses this port number value. Component ID: This field indicates the physical component that contains this Root Complex Element. Component IDs start at 1. This value is a mirror of the value in the Component ID field of all elements in this component. The value only needs to be written in one of the mirrored fields and it will be reflected everywhere that it is mirrored. 15:8 RO 01h Number of Link Entries: This field indicates the number of link entries following the Element Self Description. This field reports 1 (to Egress port only as peer-topeer capabilities in this topology are not reported). Reserved RO 0h Element Type: This field indicates the type of the Root Complex Element. 0h = root port.
23:16
R/WO 00h
7:4 3:0
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8.1.57
LE1D--Link Entry 1 Description (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 150h 00000000h RO, R/WO 32 bits
This register provides the First part of a Link Entry that declares an internal link to another Root Complex Element.
Bit 31:24
Access & Default RO 00h
Description Target Port Number: This field specifies the port number associated with the element targeted by this link entry (Egress Port). The target port number is with respect to the component that contains this element as specified by the target component ID. Target Component ID: This field indicates the physical or logical component that is targeted by this link entry. A value of 0 is reserved; Component IDs start at 1. This value is a mirror of the value in the Component ID field of all elements in this component. The value only needs to be written in one of the mirrored fields and it will be reflected everywhere that it is mirrored.
23:16
R/WO 00h
15:2 1 0 RO 0b R/WO 0b
Reserved Link Type: This field indicates that the link points to memory-mapped space (for RCRB). The link address specifies the 64-bit base address of the target RCRB. Link Valid: 0 = Link Entry is not valid and will be ignored. 1 = Link Entry specifies a valid link.
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LE1A--Link Entry 1 Address (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 158h 0000000000000000h R/WO 64 bits
This register provides the second part of a Link Entry that declares an internal link to another Root Complex Element.
Bit 63:32 31:12 11:0 R/WO 0 0000h Access & Default Reserved Link Address: This field indicates memory-mapped base address of the RCRB that is the target element (Egress Port) for this link entry. Reserved Description
8.1.59
PEGSSTS--PCI Express*-G Sequence Status (D1:F0)
PCI Device: Address Offset: Default Value: Access: Size: 1 218h 0000000000000FFFh RO 64 bits
This register provides PCI Express status reporting that is required by the PCI Express specification.
Bit 63:60 59:48 RO 000h Access & Default Reserved Next Transmit Sequence Number: Value of the NXT_TRANS_SEQ counter. This counter represents the transmit Sequence number to be applied to the next TLP to be transmitted onto the Link for the first time. Reserved RO 000h Next Packet Sequence Number: Packet sequence number to be applied to the next TLP to be transmitted or re-transmitted onto the Link. Reserved RO 000h Next Receive Sequence Number: This is the sequence number associated with the TLP that is expected to be received next. Reserved RO FFFh Last Acknowledged Sequence Number: This is the sequence number associated with the last acknowledged TLP. Description
47:44 43:32 31:28 27:16 15:12 11:0
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System Address Map
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9
System Address Map
The MCH supports 4 GB of addressable memory space (see Figure 9-1) and 64 KB+3 bytes of addressable I/O space. A programmable memory address space under the 1-MB region is divided into regions that can be individually controlled with programmable attributes such as disable, read/write, write only, or read only. This section focuses on how the memory space is partitioned and what the separate memory regions are used for. I/O address space has simpler mapping and is explained near the end of this section. Addressing of memory ranges larger than 4 GB is not supported. The HREQ[4:3] FSB pins are decoded to determine whether the access is above or below 4 GB. The MCH does not support the PCI Dual Address Cycle (DAC) Mechanism, PCI Express 64-bit prefetchable memory transactions, or any other addressing mechanism that allows addressing of greater than 4 GB on either the DMI or PCI Express interface. The MCH does not limit system memory space in hardware. There is no hardware lock to stop someone from inserting more memory than is addressable. In the following sections, it is assumed that all of the compatibility memory ranges reside on the DMI. The exception to this rule is VGA ranges that may be mapped to PCI Express or DMI. In the absence of more specific references, cycle descriptions referencing PCI should be interpreted as the DMI/PCI, while cycle descriptions referencing PCI Express are related to the PCI Express bus. The MCH does not remap APIC or any other memory spaces above TOLUD (Top of Low Usable DRAM). The TOLUD register is set to the appropriate value by BIOS. * Device 0 EPBAR - Egress port registers. Necessary for setting up VC1 as an isochronous channel using time based weighted round robin arbitration. (4-KB window) MCHBAR - Memory mapped range for internal MCH registers. For example, memory buffer register controls. (16-KB window) PCIEXBAR - Flat memory-mapped address space to access device configuration registers. This mechanism can be used to access PCI configuration space (0h-FFh) and Extended configuration space (100h-FFFh) for PCI Express devices. This enhanced configuration access mechanism is defined in the PCI Express specification. (256-MB window) DMIBAR -This window is used to access registers associated with the MCH/ICH6 (DMI) register memory range. (4-KB window) IFPBAR - Any write to this window will trigger a flush of the MCH's Global Write Buffer to let software guarantee coherency between writes from an isochronous agent and writes from the processor (4-KB window). * Device 1: Function 0: MBASE1/MLIMIT1 - PCI Express port non-prefetchable memory access window. PMBASE1/PMLIMIT1 - PCI Express port prefetchable memory access window. IOBASE1/IOLIMIT1 - PCI Express port I/O access window.
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System Address Map
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The rules for the above programmable ranges are: * ALL of these ranges MUST be unique and NON-OVERLAPPING. It is the BIOS or system designer's responsibility to limit memory population so that adequate PCI, PCI Express, High BIOS, PCI Express Memory Mapped space, and APIC memory space can be allocated. * In the case of overlapping ranges with memory, the memory decode will be given priority. * There are NO Hardware Interlocks to prevent problems in the case of overlapping ranges. * Accesses to overlapped ranges may produce indeterminate results. * The only peer-to-peer cycles allowed below the top of memory (register TOLUD) are DMI to PCI Express VGA range writes. Figure 9-1 shows the system memory address map in a simplified form. Figure 9-1. System Address Ranges
4 GB
PCI Memory Address Range (Subtractively decoded to DMI)
Device 0 Bars (EPBAR, MCHBAR, PCIEXBAR, DMIBAR)
Device 1 Bars (MBASE1/ MLIMIT1, PMBASE1/ PMLIMIT1)
TOLUD
Main Memory Address Range
Independently Programmable Non-Overlapping Windows
1 MB Legacy Address Range 0
Sys_Address_Ranges
9.1
Legacy Address Range
This area is divided into the following address regions: * 0 - 640 KB: DOS Area * 640 - 768 KB: Legacy Video Buffer Area * 768 - 896 KB in 16-KB sections (total of 8 sections): Expansion Area * 896 - 960 KB in 16-KB sections (total of 4 sections): Extended System BIOS Area * 960-KB - 1-MB Memory: System BIOS Area
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Figure 9-2. Microsoft MS-DOS* Legacy Address Range
000F_FFFFh 000F_0000h 000E_FFFFh 000E_0000h 000D_FFFFh Expansion Area 128KB (16KBx8) 000C_0000h 000B_FFFFh Legacy Video Area (SMM Memory) 128KB 000A_0000h 0009_FFFFh 640KB 768KB System BIOS (Upper) 64KB Extended System BIOS (Lower) 64KB (16KBx4) 1MB 960KB 896KB
DOS Area
0000_0000h
9.1.1
DOS Range (0h - 9_FFFFh)
The DOS area is 640 KB (0000_0000h - 0009_FFFFh) in size and is always mapped to the main memory controlled by the MCH.
9.1.2
Legacy Video Area (A_0000h-B_FFFFh)
The legacy 128-KB VGA memory range, frame buffer, (000A_0000h - 000B_FFFFh) can be mapped to PCI Express and/or to the DMI. The appropriate mapping is programmable. Based on the programming, priority for VGA mapping is constant. The MCH always decodes internally mapped devices first. The MCH always positively decodes internally mapped devices, namely the PCI Express. Subsequent decoding of regions mapped to PCI Express or the DMI depends on the programming. This region is also the default for SMM space.
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Compatible SMRAM Address Range (A_0000h-B_FFFFh)
When compatible SMM space is enabled, SMM-mode processor accesses to this range are routed to physical system DRAM at 000A_0000h-000B_FFFFh. Non-SMM-mode processor accesses to this range are considered to be to the Video Buffer Area as described above. PCI Express and DMI originated cycles to enabled SMM space are not allowed. PCI Express and DMI initiated cycles are attempted as peer cycles, and will master abort on PCI if no external VGA device claims them.
Monochrome Adapter (MDA) Range (B_0000h-B_7FFFh)
Legacy support requires the ability to have a second graphics controller (monochrome) in the system. Accesses in the standard VGA range are forwarded to PCI Express or the DMI (depending on the programming of the on-chip registers). Since the monochrome adapter may be mapped to any one of these devices, the MCH must decode cycles in the MDA range (000B_0000h - 000B_7FFFh) and forward either PCI Express or the DMI. In addition to the memory range B0000h to B7FFFh, the MCH decodes I/O cycles at 3B4h, 3B5h, 3B8h, 3B9h, 3BAh and 3BFh and forwards them to the either PCI Express, and/or the DMI.
9.1.3
Expansion Area (C_0000h-D_FFFFh)
This 128-KB ISA Expansion region (000C_0000h - 000D_FFFFh) is divided into eight, 16-KB segments. Each segment can be assigned one of four read/write states: read only, write only, read/write, or disabled. Typically, these blocks are mapped through the MCH and are subtractively decoded to ISA space. Memory that is disabled is not remapped. Non-snooped accesses from PCI Express or DMI to this region are always sent to main memory.
Table 9-1. Expansion Area Memory Segments
Memory Segments 0C0000h-0C3FFFh 0C4000h-0C7FFFh 0C8000h-0CBFFFh 0CC000h -0CFFFFh 0D0000h-0D3FFFh 0D4000h-0D7FFFh 0D8000h-0DBFFFh 0DC000h-0DFFFFh Attributes W/R W/R W/R W/R W/R W/R W/R W/R Comments Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS
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9.1.4
Extended System BIOS Area (E_0000h-E_FFFFh)
This 64-KB area (000E_0000h-000E_FFFFh) is divided into four, 16-KB segments. Each segment can be assigned independent read and write attributes so it can be mapped either to main DRAM or to the DMI. Typically, this area is used for RAM or ROM. Memory segments that are disabled are not remapped elsewhere. Non-snooped accesses from PCI Express or DMI to this region are always sent to main memory.
Table 9-2. Extended System BIOS Area Memory Segments
Memory Segments 0E0000h-0E3FFFh 0E4000h-0E7FFFh 0E8000h-0EBFFFh 0EC000h-0EFFFFh Attributes W/R W/R W/R W/R Comments BIOS Extension BIOS Extension BIOS Extension BIOS Extension
9.1.5
System BIOS Area (F_0000h-F_FFFFh)
This area is a single, 64-KB segment (000F_0000h - 000F_FFFFh). This segment can be assigned read and write attributes. It is by default (after reset) read/write disabled and cycles are forwarded to the DMI. By programming the read/write attributes, the MCH can "shadow" BIOS into main memory. When disabled, this segment is not remapped. Non-snooped accesses from PCI Express or DMI to this region are always sent to main memory.
Table 9-3. System BIOS Area Memory Segments
Memory Segments 0F0000h-0FFFFFh Attributes WE RE Comments BIOS Area
9.1.6
Programmable Attribute Map (PAM) Memory Area Details
The 13 sections from 768 KB to 1 MB comprise what is also known as the PAM memory area. The MCH does not handle IWB (Implicit Write-Back) cycles targeting DMI. Since all memory residing on DMI should be set as non-cacheable, there will normally not be IWB cycles targeting DMI. However, DMI becomes the default target for processor and DMI originated accesses to disabled segments of the PAM region. If the MTRRs covering the PAM regions are set to WB or RC, it is possible to get IWB cycles targeting DMI. This may occur for DMI-originated cycles to disabled PAM regions. Note: For example, assume that a particular PAM region is set for "Read Disabled" and the MTRR associated with this region is set to WB. A DMI master generates a memory read targeting the PAM region. A snoop is generated on the FSB and the result is an IWB. Since the PAM region is
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"Read Disabled", the default target for the memory read becomes DMI. The IWB associated with this cycle will cause the MCH to hang.
9.2
Main Memory Address Range (1 MB to TOLUD)
This address range extends from 1 MB to the top of physical memory that is permitted to be accessible by the MCH (as programmed by BIOS). All accesses to addresses within this range will be forwarded by the MCH to the main memory unless they fall into the optional TSEG or optional ISA Hole. The MCH provides a maximum main memory address decode space of 4 GB. The MCH does not remap APIC or PCI Express memory space. This means that as the amount of physical memory populated in the system reaches 4 GB, there will be physical memory that exists, yet nonaddressable; therefore, this memory is unusable by the system. The MCH does not limit main memory address space in hardware.
Figure 9-3. Main Memory Address Range
FFFF_FFFFh 4 GB Maximum Flash APIC Contains programmable windows, ICH6/PCI ranges.
PCI Memory Range TOLUD (Optional) TSEG (1 MB / 2 MB / 8 MB, optional)
Main Memory 0100_000h 00F0_000h ISA Hole (optional) Main Memory 0010_000h DOS Compatibility Memory 0h 0 MB
Main_Mem_Addr
16 MB 15 MB
1 MB
9.2.1
ISA Hole (15 MB-16 MB)
BIOS can create a hole at 15 MB-16 MB. Accesses within this hole are forwarded to the DMI. The range of physical main memory disabled by opening the hole is not remapped to the top of the memory; that physical main memory space is not accessible. This 15 MB-16 MB hole is an optionally enabled ISA hole.
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9.2.2
TSEG
TSEG is optionally 1 MB, 2 MB, or 8 MB in size. SMM-mode processor accesses to enabled TSEG access the physical DRAM at the same address. Non-processor originated accesses are not allowed to SMM space. PCI Express and DMI originated cycles to enabled SMM space are handled as invalid cycle type with reads and writes to location 0 and byte enables turned off for writes. When the extended SMRAM space is enabled, processor accesses to the TSEG range without SMM attribute or without WB attribute are also forwarded to memory as invalid accesses. Non-SMM-mode write-back cycles that target TSEG space are completed to main memory for cache coherency. When SMM is enabled, the maximum amount of memory available to the system is equal to the amount of physical main memory minus the value in the TSEG register which is fixed at 1 MB, 2 MB or 8 MB.
9.2.3
Pre-allocated Memory
Voids of physical addresses that are not accessible as general system memory and reside within system memory address range (< TOLUD) are created for SMM-mode and legacy VGA graphics compatibility. It is the responsibility of BIOS to properly initialize these regions. Table 9-4 details the location and attributes of the regions.
Table 9-4. Pre-Allocated Memory Example for 64-MB DRAM and 1-MB TSEG
Memory Segments 0000_0000h - 03DF_FFFFh 03E0_0000h - 03EF_FFFFh 03F0_0000h - 03FF_FFFFh Attributes R/W SMM Mode Only processor reads R/W Comments Available system memory 62 MB TSEG Address Range and Pre-allocated memory Pre-allocated Graphics VGA memory.
9.3
PCI Memory Address Range (TOLUD - 4 GB)
This address range, from the top of physical memory to 4 GB (top of addressable memory space supported by the MCH) is normally mapped via the DMI to PCI. Note: AGIP Aperture no longer exists with PCI Express.
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Figure 9-4. PCI Memory Address Range
FFFF_FFFFh High BIOS FFE0_0000h DMI Interface (subtractively decode) FEF0_0000h FEE0_0000h FED0_0000h FEC8_0000h FEC0_0000h DMI Interface (subtractively decode) F000_0000h PCI Express Configuration Space E000_0000h 4 GB - 512 MB DMI Interface (subtractively decode) Programmable windows, graphics ranges, PCI Express* Port could be here TOLUD
PCI_Address_Ranges_G-P-only
4 GB 4 GB - 2 MB
4 GB - 17 MB FSB Interrupts DMI Interface (subtractively decode) Local (processor) APIC I/O APIC 4 GB - 20 MB 4 GB - 18 MB 4 GB - 19 MB Optional HSEG FEDA_0000h to FEDB_FFFFh
4 GB - 256 MB Possible address range (Not guaranteed)
9.3.1
APIC Configuration Space (FEC0_0000h-FECF_FFFFh)
This range is reserved for APIC configuration space. The I/O APIC(s) usually reside in the ICH6 portion of the chipset, but may also exist as stand-alone components. The IOAPIC spaces are used to communicate with IOAPIC interrupt controllers that may be populated in the system. Since it is difficult to relocate an interrupt controller using plug-and-play software, fixed address decode regions have been allocated for them. Processor accesses to the default IOAPIC region (FEC0_0000h to FEC7_FFFFh) are always forwarded to DMI.
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9.3.2
HSEG (FEDA_0000h-FEDB_FFFFh)
This optional segment from FEDA_0000h to FEDB_FFFFh provides a remapping window to SMM memory. It is sometimes called the High SMM memory space. SMM-mode processor accesses to the optionally enabled HSEG are remapped to 000A_0000h - 000B_FFFFh. NonSMM-mode processor accesses to enabled HSEG are considered invalid and are terminated immediately on the FSB. The exceptions to this rule are Non-SMM-mode write-back cycles that are remapped to SMM space to maintain cache coherency. PCI Express and DMI originated cycles to enabled SMM space are not allowed. Physical main memory behind the HSEG transaction address is not remapped and is not accessible. All cacheline writes with WB attribute or Implicit write backs to the HSEG range are completed to DRAM like an SMM cycle.
9.3.3
FSB Interrupt Memory Space (FEE0_0000-FEEF_FFFF)
The FSB Interrupt space is the address used to deliver interrupts to the FSB. Any device on PCI Express or DMI may issue a memory write to 0FEEx_xxxxh. The MCH will forward this memory write along with the data to the FSB as an Interrupt Message Transaction. The MCH terminates the FSB transaction by providing the response and asserting HTRDY#. This memory write cycle does not go to main memory.
9.3.4
High BIOS Area
The top 2 MB (FFE0_0000h -FFFF_FFFFh) of the PCI memory address range is reserved for system BIOS (High BIOS), extended BIOS for PCI devices, and the A20 alias of the system BIOS. The processor begins execution from the High BIOS after reset. This region is mapped to the DMI so that the upper subset of this region aliases to the 16-MB-256-KB range. The actual address space required for the BIOS is less than 2 MB, but the minimum processor MTRR range for this region is 2 MB; thus, that full 2 MB must be considered.
9.3.5
PCI Express* Configuration Address Space
A configuration register defines the base address for the 256-MB block of addresses below top of addressable memory (4 GB) for the configuration space associated with all devices and functions that are potentially a part of the PCI Express root complex hierarchy. This range will be aligned to a 256-MB boundary. BIOS must assign this address range such that it will not conflict with any other address ranges.
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9.3.6
PCI Express* Graphics Attach
The MCH can be programmed to direct memory accesses to the PCI Express interface when addresses are within either of two programmed ranges specified via registers in the MCH's Device 1 configuration space. * The first range is controlled via the Memory Base Register (MBASE) and Memory Limit Register (MLIMIT) registers. * The second range is controlled via the Prefetchable Memory Base (PMBASE) and Prefetchable Memory Limit (PMLIMIT) registers. The MCH positively decodes memory accesses to PCI Express memory address space as defined by the following equations: Memory_Base_Address Address Memory_Limit_Address Prefetchable_Memory_Base_Address Address Prefetchable_Memory_Limit_Address It is essential to support a separate Prefetchable range to apply USWC attribute (from the processor point of view) to that range. The USWC attribute is used by the processor for write combining. Note: The programmable ranges are used to allocate memory address space for any PCI Express devices sitting on PCI Express that require such a window. The PCICMD1 register can override the routing of memory accesses to PCI Express. In other words, the memory access enable bit must be set in the device 1 PCICMD1 register to enable the memory base/limit and prefetchable base/limit windows.
9.3.7
AGP DRAM Graphics Aperture
Unlike AGP4x, PCI Express has no concept of aperture for PCI Express devices. As a result, there is no need to translate addresses from PCI Express. Therefore, the MCH has no APBASE and APSIZE registers.
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9.4
System Management Mode (SMM)
System Management Mode uses main memory for System Management RAM (SMM RAM). The MCH supports: Compatible SMRAM (C_SMRAM), High Segment (HSEG), and Top of Memory Segment (TSEG). System Management RAM space provides a memory area that is available for the SMI handlers and code and data storage. This memory resource is normally hidden from the system OS so that the processor has immediate access to this memory space upon entry to SMM. MCH provides three SMRAM options: * Below 1-MB option that supports compatible SMI handlers. * Above 1-MB option that allows new SMI handlers to execute with write-back cacheable SMRAM. * Optional TSEG area of 1 MB, 2 MB, or 8 MB in size. The above 1-MB solutions require changes to compatible SMRAM handler's code to properly execute above 1 MB. Note: DMI and PCI Express masters are not allowed to access the SMM space.
9.4.1
SMM Space Definition
SMM space is defined by its addressed SMM space and its DRAM SMM space. The addressed SMM space is defined as the range of bus addresses used by the processor to access SMM space. DRAM SMM space is defined as the range of physical main memory locations containing the SMM code. SMM space can be accessed at one of three transaction address ranges: Compatible, High, and TSEG. The Compatible and TSEG SMM space is not remapped; therefore, the addressed and DRAM SMM space is the same address range. Since the High SMM space is remapped, the addressed and DRAM SMM space are different address ranges. Note that the High DRAM space is the same as the Compatible Transaction Address space. The following table describes three unique address ranges: * Compatible Transaction Address * High Transaction Address * TSEG Transaction Address
SMM Space Enabled Compatible (C) High (H) TSEG (T)
Transaction Address Space 000A_0000h to 000B_FFFFh FEDA_0000h to FEDB_FFFFh (TOLUD-STOLEN-TSEG) to TOLUD-STOLEN
DRAM Space (DRAM) 000A_0000h to 000B_FFFFh 000A_0000h to 000B_FFFFh (TOLUD-STOLEN-TSEG) to TOLUD-STOLEN
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9.4.2
SMM Space Restrictions
If any of the following conditions are violated, the results of SMM accesses are unpredictable and may cause the system to hang: * The Compatible SMM space must not be set-up as cacheable. * High or TSEG SMM transaction address space must not overlap address space assigned to system main memory, or to any "PCI" devices (including DMI, PCI Express, and graphics devices). This is a BIOS responsibility. * Both D_OPEN and D_CLOSE capability must not be enabled at the same time. * When TSEG SMM space is enabled, the TSEG space must not be reported to the OS as available main memory. This is a BIOS responsibility. * Any address translated through the GMADR TLB must not target main memory from A_0000-F_FFFF.
9.4.3
SMM Space Combinations
When High SMM is enabled, the Compatible SMM space is effectively disabled. Processor originated accesses to the Compatible SMM space are forwarded to PCI Express if this VGA capability is enabled; otherwise, they are forwarded to the DMI. PCI Express and DMI originated accesses are never allowed to access SMM space.
Table 9-5. SMM Space Table
Global Enable G_SMRAME 0 1 1 1 1 High Enable H_SMRAM_EN X 0 0 1 1 TSEG Enable TSEG_EN X 0 1 0 1 Compatible (C) Range Disable Enable Enable Disabled Disabled High (H) Range Disable Disable Disable Enable Enable TSEG (T) Range Disable Disable Enable Disable Enable
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9.4.4
SMM Control Combinations
The G_SMRAME bit provides a global enable for all SMM memory. The D_OPEN bit allows software to write to the SMM ranges without being in SMM mode. BIOS software can use this bit to initialize SMM code at powerup. The D_LCK bit limits the SMM range access to only SMM mode accesses. The D_CLS bit causes SMM data accesses to be forwarded to the DMI or PCI Express. The SMM software can use this bit to write to video memory while running SMM code out of DRAM.
Table 9-6. SMM Control Table
G_SMRAME 0 1 1 1 1 1 1 1 1 D_LCK x 0 0 0 0 0 1 1 1 D_CLS X X 0 0 1 1 X 0 1 D_OPEN x 0 0 1 0 1 x x x CPU in SMM Mode x 0 1 x 1 x 0 1 1 SMM Code Access Disable Disable Enable Enable Enable Invalid Disable Enable Enable SMM Data Access Disable Disable Enable Enable Disable Invalid Disable Enable Disable
9.4.5
SMM Space Decode and Transaction Handling
Only the processor is allowed to access SMM space. PCI Express and DMI originated transactions are not allowed to SMM space.
9.4.6
Processor WB Transaction to an Enabled SMM Address Space
Processor write-back transactions (HREQ1# = 0) to enabled SMM address space must be written to the associated SMM DRAM, even though the space is not open and the transaction is not performed in SMM mode. This ensures SMM space cache coherency when cacheable extended SMM space is used.
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9.4.7
SMM Access through GTT TLB
Accesses through GTT TLB address translation to enabled SMM DRAM space are not allowed. Writes will be routed to memory address 0h with byte enables de-asserted and reads will be routed to memory address 0h. If a GTT TLB translated address hits enabled SMM DRAM space, an Invalid Translation Table Entry Flag is reported to BIOS. PCI Express and DMI originated accesses are never allowed to access SMM space directly or through the GTT TLB address translation. If a GTT TLB translated address hits enabled SMM DRAM space, an Invalid Translation Table Entry Flag is reported to BIOS. PCI Express and DMI write accesses through the graphics memory range set up by BIOS will be snooped. If, when translated, the resulting physical address is to enabled SMM DRAM space, the request will be remapped to address 0h with de-asserted byte enables. PCI Express and DMI read accesses to the graphics memory range set up by BIOS are not supported; therefore, users/systems will be remapped to address 0h. The read will complete with UR (unsupported request) completion status. GTT fetches are always decoded (at fetch time) to ensure they are not in SMM (actually, anything above base of TSEG or 640 KB-1 MB). Thus, they will be invalid and go to address 0h. This is not specific to PCI Express or DMI; it applies to the processor. Also, since the graphics memory range snoop would not be directly to SMM space, there would not be a writeback to SMM. In fact, the writeback would also be invalid (because it uses the same translation) and goes to address 0h.
9.4.8
Memory Shadowing
Any block of memory that can be designated as "read only" or "write only" can be "shadowed" into MCH main memory. Typically, this is done to allow ROM code to execute more rapidly out of main DRAM memory. ROM is used as read-only during the copy process while main DRAM memory at the same time is designated write-only. After copying, the main DRAM memory is designated read-only so that ROM is shadowed. Processor bus transactions are routed accordingly.
9.4.9
I/O Address Space
The MCH does not support the existence of any other I/O devices beside itself on the processor bus. The MCH generates either DMI or PCI Express bus cycles for all processor I/O accesses that it does not claim. Within the host bridge, the MCH contains two internal registers in the processor I/O space. These locations are used to implement a configuration space access mechanism. The processor allows 64 KB+3 bytes to be addressed within the I/O space. The MCH propagates the processor I/O address without any translation on to the destination bus; therefore, providing addressability for 64 KB+3 byte locations. Note that the upper 3 locations can be accessed only during I/O address wrap-around when processor bus HA16# address signal is asserted. HA16# is asserted on the processor bus when an I/O access is made to 4 bytes from address 0FFFDh, 0FFFEh, or 0FFFFh. HA16# is also asserted when an I/O access is made to 2 bytes from address 0FFFFh.
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The I/O accesses (other than ones used for configuration space access) are forwarded normally to the DMI bus unless they fall within the PCI Express I/O address range as defined by the mechanisms explained below. I/O writes are not posted. Memory writes to the ICH6 or PCI Express are posted. The MCH responds to I/O cycles initiated on PCI Express or DMI with a UR status. Upstream I/O cycles and configuration cycles should never occur. If one does occur, the request will route as a read to memory address 0h so a completion is naturally generated (whether the original request was a read or write). The transaction will complete with a UR completion status. For Pentium 4 processors, I/O reads that lie within 8-byte boundaries but cross 4-byte boundaries are issued from the processor as 1 transaction. The MCH will break this into 2 separate transactions. This has not been done on previous chipsets. I/O writes that lie within 8-byte boundaries but cross 4-byte boundaries are assumed to be split into 2 transactions by the processor.
9.4.10
PCI Express* I/O Address Mapping
The MCH can be programmed to direct non-memory (I/O) accesses to the PCI Express bus interface when processor-initiated I/O cycle addresses are within the PCI Express I/O address range.
9.4.11
MCH Decode Rules and Cross-Bridge Address Mapping
The following are MCH decode rules and cross-bridge address mapping used in this chipset: * VGAA = 000A_0000h - 000A_FFFFh * MDA = 000B_0000h - 000B_7FFFh * VGAB = 000B_8000h - 000B_FFFFh * MAINMEM = 0100_0000 to TOLUD
9.4.12
Legacy VGA and I/O Range Decode Rules
The legacy 128-KB VGA memory range 000A_0000h-000B_FFFFh can be mapped to PCI Express (Device 1), and/or to the DMI depending on BIOS programming. Priority for VGA mapping is constant in that the MCH always decodes internally mapped devices first. The MCH always positively decodes internally mapped devices, namely the PCI Express.
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10
10.1
Functional Description
This chapter describes the MCH interfaces and major functional units.
Host Interface
The MCH supports the Pentium 4 processor subset of the Enhanced Mode Scaleable Bus. The cache line size is 64 bytes. Source synchronous transfer is used for the address and data signals. The address signals are double pumped, and a new address can be generated every other bus clock. At 200 MHz bus clock, the address signals run at 400 MT/s for a maximum address queue rate of 66/100 million addresses/sec. The data is quad pumped and an entire 64 byte cache line can be transferred in two bus clocks. At 200 MHz bus clock, the data signals run at 800 MT/s for a maximum bandwidth of 6.4 GB/s. The FSB interface supports up to 12 simultaneous outstanding transactions. The MCH supports only one outstanding deferred transaction on the FSB.
10.1.1
FSB GTL+ Termination
The MCH integrates GTL+ termination resistors on die. Also, approximately 2.8 pf (fast) - 3.3 pf (slow) per pad of on die capacitance will be implemented to provide better FSB electrical performance.
10.1.2
FSB Dynamic Bus Inversion
The MCH supports Dynamic Bus Inversion (DBI) when driving and when receiving data from the processor. DBI limits the number of data signals that are driven to a low voltage on each quad pumped data phase. This decreases the worst-case power consumption of the MCH. HDINV[3:0]# indicate if the corresponding 16 bits of data are inverted on the bus for each quad pumped data phase:
HDINV[3:0]# HDINV0# HDINV1# HDINV2# HDINV3# Data Bits HD[15:0]# HD[31:16]# HD[47:32]# HD[63:48]#
When the processor or the MCH drives data, each 16-bit segment is analyzed. If more than 8 of the 16 signals would normally be driven low on the bus, the corresponding HDINV# signal will be asserted and the data will be inverted prior to being driven on the bus. When the processor or the MCH receives data, it monitors HDINV[3:0]# to determine if the corresponding data segment should be inverted.
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10.1.3
APIC Cluster Mode Support
This is required for backwards compatibility with existing software, including various operating systems. As one example, beginning with Microsoft Windows 2000 there is a mode (boot.ini) that allows an end user to enable the use of cluster addressing support of the APIC. The MCH supports three types of interrupt re-direction: * Physical * Flat-Logical * Clustered-Logical
10.2
System Memory Controller
This section describes the MCH system memory interface for DDR2 memory. The MCH supports DDR2 memory and either one or two DIMMs per channel.
10.2.1
Memory Organization Modes
The system memory controller supports two styles of memory organization (Interleaved and Asymmetric). Rules for populating DIMM slots are included in this chapter.
Interleaved Mode
This mode provides maximum performance on real applications. Addresses are ping-ponged between the channels, and the switch happens after each cache line (64 byte boundary). If two consecutive cache lines are requested, both may be retrieved simultaneously, since they are guaranteed to be on opposite channels. The drawbacks of Interleaved Mode are that the system designer must populate both channels of memory such that they have equal capacity, but the technology and device width may vary from one channel to the other. Refer to Figure 10-1 for further clarification.
Asymmetric Mode
This mode trades performance for system design flexibility. Unlike the previous mode, addresses start in channel A and stay there until the end of the highest rank in channel A; then, addresses continue from the bottom of channel B to the top. Real world applications are unlikely to make requests that alternate between addresses that sit on opposite channels with this memory organization, so in most cases, bandwidth will be limited to that of a single channel. The system designer is free to populate or not to populate any rank on either channel, including either degenerate single channel case. Refer to Figure 10-1 for further clarification.
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Figure 10-1. System Memory Styles
Dual Channel Interleaved (channels do not have to match) CL TOM CH B CH A TOM CH B CH B0 CH A TOM CH A or CH B CH B CH A CH B CH A 0 Scheme XOR Bit 6 => CL
Sys_Mem_Styles
Single Channel
Dual Channel Asymmetric (channels do not have to match) CL
CL
CH B TOM
CH A
CH A0 0
Table 10-1. Sample System Memory Organization with Interleaved Channels
Rank Channel A population 0 MB 256 MB 512 MB 512 MB Cumulative top address in Channel A 2560 MB 2560 MB 2048 MB 1024 MB Channel B population 0 MB 256 MB 512 MB 512 MB Cumulative top address in Channel B 2560 MB 2560 MB 2048 MB 1024 MB
3 2 1 0
Table 10-2. Sample System Memory Organization with Asymmetric Channels
Rank Channel A population 0 MB 256 MB 512 MB 512 MB Cumulative top address in Channel A 1280 MB 1280 MB 1024 MB 512 MB Channel B population 0 MB 256 MB 512 MB 512 MB Cumulative top address in Channel B 2560 MB 2560 MB 2304 MB 1792 MB
3 2 1 0
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10.3
System Memory Configuration Register Overview
The configuration registers located in the PCI configuration space of the MCH control the system memory operation. Following is a brief description of configuration registers. * DRAM Rank Boundary (CxDRBy): The x represents a channel, either A (where x = 0) or B (where x = 1). The y represents a rank, 0 through 3. DRB registers define the upper addresses for a rank of DRAM devices in a channel. When the MCH is configured in asymmetric mode, each register represents a single rank. When the MCH is configured in a dual interleaved mode, each register represents a pair of corresponding ranks in opposing channels. There are 4 DRB registers for each channel. * DRAM Rank Architecture (CxDRAy): The x represents a channel, either A (where x = 0) or B (where x = 1). The y represents a rank, 0 through 3. DRA registers specify the architecture features of each rank of devices in a channel. The only architecture feature specified is page size. When the MCH is configured in asymmetric mode, each DRA represents a single rank in a single channel. When the MCH is configured in a dual-channel lock-step or interleaved mode, each DRA represents a pair of corresponding ranks in opposing channels. There are 4 DRA registers per channel. Each requires only 3 bits, so there are two DRAs packed into a byte. * Clock Configuration (CLKCFG): Specifies DRAM frequency. The same clock frequency will be driven to all DIMMs. * DRAM Timing (CxDRTy): The x represents a channel, A (where x = 0) or B (where x = 1). A second register for a channel is differentiated by y, A or B. The DRT registers define the timing parameters for all devices in a channel. The BIOS programs this register with "least common denominator" values after reading the SPD registers of each DIMM in the channel. * DRAM Control (CxDRCy): The x represents a channel, A (where x = 0) or B (where x = 1). A second register for a channel is differentiated by y, A or B. DRAM refresh mode, rate, and other controls are selected here.
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10.3.1
DRAM Technologies and Organization
All standard 256-Mb, 512-Mb, and 1-Gb technologies and addressing are supported for x16 and x8 devices. * All supported DDR2 devices have 4 or 8 banks. * The MCH supports various page sizes. Page size is individually selected for every rank. * 4 KB, 8 KB, and 16 KB for asymmetric, interleaved, or single channel modes. * The DRAM sub-system supports single or dual channels, 64b wide per channel for non-ECC and 72b wide per channel with ECC. * There can be a maximum of 4 ranks populated (2 Double Sided DIMMs) per channel. * Mixed mode Double Sided DIMMs (x8 and x16 on the same DIMM) are not supported * By using 1-Gb technology, the largest memory capacity is 8 GB 32M rows/bank * 4 banks/device * 8 columns * 8 devices/rank * 4 ranks/channel * 2 channel * 1b/(row*column) * 1G/1024M * 1B/8b = 8 GB. Though it is possible to put 8 GB in system by stuffing both channels this way, the MCH is still limited to 4 GB of addressable space due to the number of address pins on the FSB. * By using 256Mb technology, the smallest memory capacity is 128 MB (4M rows/bank * 4banks/device * 16 columns * 4 devices/rank * 1 rank * 1B/8b =128 MB)
10.3.1.1
Rules for Populating DIMM Slots
* In all modes, the frequency of system memory will be the lowest frequency of all DIMMs in the system, as determined through the SPD registers on the DIMMs. * In the Single Channel mode, any DIMM slot within the channel may be populated in any order. Either channel may be used. To save power, do not populate the unused channel. * In Dual Channel Asymmetric mode, any DIMM slot may be populated in any order. * In Dual Channel Interleaved mode, any DIMM slot may be populated in any order, but the total memory in each channel must be the same.
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10.3.1.2
System Memory Supported Configurations
The MCH supports the 256-Mbit, 512-Mbit and 1-Gbit technology-based DIMMs from Table 10-3.
Table 10-3. DDR2 DIMM Supported Configurations
Technology Configuration # of Row Address Bits 13 13 13 13 14 14 14 13 14 # of Column Address Bits # of Bank Address Bits 2 2 2 2 2 2 2 3 3 Page Size Rank Size
256 Mbit 256 Mbit 512 Mbit 512 Mbit 512 Mbit 1 Gbit 1 Gbit 1 Gbit 1 Gbit
16M X 16 32M X 8 32M X 16 64M X 8 64M X 8 64M X 16 128M X 8 64M X 16 128M X 8
9 10 10 11 10 10 11 10 10
4K 8K 8K 16K 8K 8K 16K 8K 8K
128 MB 256 MB 256 MB 512 MB 512 MB 512 MB 1 GB 512 MB 1 GB
10.3.1.3
Main Memory DRAM Address Translation and Decoding
Table 10-4 and Table 10-5 specify the host interface to memory interface address multiplex for the MCH. Refer to the details of the various DIMM configurations as described in Table 10-3. The address lines specified in the column header refer to the host (processor) address lines.
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Table 10-4. DRAM Address Translation (Single Channel/Dual Asymmetric Mode)
Rank Size Page Size Banks Tech
31
30
29
28
27
26 r10
25 r9 r9 r9 r9 r9 r9 r9 r9 r9 r9
24 r8 r8 r8 r8 r8 r8 r8 r8 r8 r8
23 r7 r7 r7 r7 r7 r7 r7 r7 r7 r7
22 r6 r6 r6 r6 r6 r6 r6 r6 r6 r6
21 r5 r5 r5 r5 r5 r5 r5 r5 r5 r5
20 r4 r4 r4 r4 r4 r4 r4 r4 r4 r4
19 r3 r3 r3 r3 r3 r3 r3 r3 r3 r3
18 r2 r2 r2 r2 r2 r2 r2 r2 r2 r2
17 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1
16 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0
15 r11 r11 r11 b0 r11 r11 r11 b0 b0 b0
14 r12 b1 b1 b1 b1 b1 b1 b1 b1 b1
13 b0 b0 b0
12 b1 c9 c9
11 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8
10 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7
9 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6
8 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5
7 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4
6 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3
5 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2
4 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1
3 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0
256 Mb x16 256 Mb x8 512 Mb x16 512 Mb x8 512 Mb x16 512 Mb x8 1 Gb x16 1 Gb x8 1 Gb x16 1 Gb x8
4i 4i 4i 4i 4i 4i 4i 4i 8i 8i
4 KB 8 KB 8 KB 16 KB 8 KB 8 KB 8 KB 16 KB 8 KB 8 KB
128 MB 256 MB 256 MB 512 MB 256 MB 512 MB 512 MB 1 GB 512 MB 1 GB r13 r13 r13 r13 r11 r11 r11 r11 r12 r12 r12 r12 r12 r12 r12 r12 r12
r10 r10 r10 r10 r10 r10 r10 r10 r10
c11 c9 b0 b0 b0 c9 c9 c9
c11 c9 b2 b2 c9 c9
NOTES: 1. b - `bank' select bit 2. c - `column' address bit 3. r - `row' address bit
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Table 10-5. DRAM Address Translation (Dual Channel Symmetric Mode)
Rank Size Page Size Banks Tech
31
30
29
28
27 r10
26 r9 r9 r9 r9 r9 r9 r9 r9 r9 r9
25 r8 r8 r8 r8 r8 r8 r8 r8 r8 r8
24 r7 r7 r7 r7 r7 r7 r7 r7 r7 r7
23 r6 r6 r6 r6 r6 r6 r6 r6 r6 r6
22 r5 r5 r5 r5 r5 r5 r5 r5 r5 r5
21 r4 r4 r4 r4 r4 r4 r4 r4 r4 r4
20 r3 r3 r3 r3 r3 r3 r3 r3 r3 r3
19 r2 r2 r2 r2 r2 r2 r2 r2 r2 r2
18 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1
17 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0
16 r11 r11 r11 b0 r11 r11 r11 b0 b0 b0
15 r12 b1 b1 b1 b1 b1 b1 b1 b1 b1
14 b0 b0 b0
13 b1 c9 c9
12 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8
11 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7
10 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6
9 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5
8 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4
7 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3
6 h h h h h h h h h h
5 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2
4 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1
3 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0
256 Mb x16 256 Mb x8 512 Mb x16 512 Mb x8 512 Mb x16 512 Mb x8 1 Gb x16 1 Gb x8 1 Gb x16 1 Gb x8
4i 4i 4i 4i 4i 4i 4i 4i 8i 8i
4 KB 8 KB 8 KB 16 KB 4 KB 8 KB 8 KB 16 KB 4 KB 8 KB
128 MB 256 MB 256 MB 512 MB 256 MB 512 MB 512 MB 1 GB 512 MB 1 GB r13 r13 r13 r13 r11 r11 r11 r11 r12 r12 r12 r12 r12 r12 r12 r12 r12
r10 r10 r10 r10 r10 r10 r10 r10 r10
c11 c9 b0 b0 b0 c9 c9 c9
c11 c9 b2 b2 c9 c9
NOTES: 1. b - `bank' select bit 2. c - `column' address bit 3. h - channel select bit 4. r - `row' address bit
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10.3.2
DRAM Clock Generation
The MCH generates three differential clock pairs for every supported DIMM. There are a total of 6 clock pairs driven directly by the MCH to 2 DIMMs per channel.
10.3.3
Suspend to RAM and Resume
When entering the Suspend-to-RAM (STR) state, the SDRAM controller will flush pending cycles and then enter all SDRAM rows into self refresh. In STR, the CKE signals remain LOW so the SDRAM devices will perform self-refresh.
10.3.4
DDR2 On-Die Termination
On-die termination (ODT) is a feature that allows a DRAM to turn on/off internal termination resistance for each DQ, DM, DQS, and DQS# signal for x8 and x16 configurations via the ODT control signals. The ODT feature is designed to improve signal integrity of the memory channel by allowing the termination resistance for the DQ, DM, DQS, and DQS# signals to be located inside the DRAM devices themselves, instead of on the motherboard. The MCH drives out the required ODT signals, based on memory configuration and which rank is being written to or read from, to the DRAM devices on a targeted DIMM rank to enable or disable their termination resistance.
10.3.5
DDR2 Off-Chip Driver Impedance Calibration
The OCD impedance adjustment mode allows the MCH to measure and adjust the pull-up and pull-down strength of the DRAM devices. It uses a series of EMRS commands to guide the DRAM through measurement and calibration cycles. This feature is described in more detail in the JEDEC DDR2 device specification. The algorithm and sequence of the adjustment cycles is handled by software. The MCH adjusts the DRAM driver impedance by issuing OCD commands to the DIMM and looking at the analog voltage on the DQ lines.
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10.4
PCI Express*
Refer to Chapter 1 for a list of PCI Express features, and the PCI Express specification for further details. The MCH is part of a PCI Express root complex. This means it connects a host processor/memory subsystem to a PCI Express hierarchy. The PCI Express architecture is specified in layers. Compatibility with the PCI addressing model (a load-store architecture with a flat address space) is maintained to ensure that all existing applications and drivers operate unchanged. The PCI Express configuration uses standard mechanisms as defined in the PCI Plug-and-Play specification. The initial speed of 1.25 GHz (250 MHz internally) results in 2.5 Gb/s/direction that provides a 250 MB/s communications channel in each direction (500 MB/s total) that is close to twice the data rate of classic PCI per lane. Note: The PCI Express graphics port will operate in x1 mode if a non-graphics card is plugged in.
10.4.1
Transaction Layer
The upper layer of the PCI Express architecture is the Transaction Layer. The Transaction Layer's primary responsibility is the assembly and disassembly of Transaction Layer Packets (TLPs). TLPs are used to communicate transactions (such as read and write as well as certain types of events). The Transaction Layer also manages flow control of TLPs.
Note: If the MCH receives two back-to-back malformed packets, the second malformed packet is not trapped or logged. The MCH will not log or identify the second malformed packet. However, the 1st malformed TLP is logged, and is considered a Fatal Error. Link behavior is not guaranteed at that point whether a 2nd malformed TLP is detected or not.
10.4.2
Data Link Layer
The middle layer in the PCI Express stack, the Data Link Layer, serves as an intermediate stage between the Transaction Layer and the Physical Layer. Responsibilities of Data Link Layer include link management, error detection, and error correction.
10.4.3
Physical Layer
The Physical Layer includes all circuitry for interface operation, including driver and input buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), and impedance matching circuitry.
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10.5
Power Management
Power Management capabilities of the MCH include the following: * ACPI 1.0b support * ACPI S0, S3, S4, S5, C0, C1, C2, C3, C4 * Enhanced power management state transitions for increasing time the processor spends in low power states * Graphics Adapter States: D0, D3. * PCI Express Link States: L0, L0s, L1, L2/L3 Ready, L3 * PM_THRMTRIP# output * Conditional memory Self-Refresh during C2, C3, and C4 states
10.6
Clocking
The MCH has PLLs to provide the internal clocks. * Host PLL - This PLL generates the main core clocks in the host clock domain. The host PLL is used to generate memory and internal graphics core clocks. It uses the Host clock (HCLKIN) as a reference. * PCI Express PLL - This PLL generates all PCI Express related clocks, including the Direct Media Interface that connects to the ICH6. This PLL uses the 100 MHz (GCLKIN) as a reference. Figure 10-2 illustrates the various clocks in the platform.
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Figure 10-2. System Clocking Example
Diff Pair
ITP CK410 56Pin SSOP
Processor Diff Pair Processor Diff Pair Processor Diff Pair
Processor
Memory
Slot 0
Slot 1
Slot 2
Main PLL SSC
PCI Express GFX HPLL
PCI Express Diff Pair PCI Express Diff Pair
PCI Express Dif f Pair PCI Express Dif f Pair PCI Express Dev PCI Express Dev PCI Express Dev PCI Express Dev P CI Express PLL
MPLL
x16 PCI Exp
DMI
SATA PLL SSC
PCI Express Dif f Pair PCI Express Dif f Pair PCI Express Dif f Pair
MCH
SATA DiffPair
25 MHz Diff Pair
66 MHz Diff Pair
4 x1 PCI Exp
SATA PLL
P CI Express PLL
CK410 48Pin SSOP
48 MHz USB REF 14 MHz REF 14 MHz
USB PLL SIO LPC LAN AC97 TPM LPC OSC FWH LPC GlueChip Port80 PCI
LCI Bit Clock
High Def Audio Bit Clock
48/14 MHz PLL
25 MHz REF 14 MHz PCI 33 MHz PCI 33 MHz PCI 33 MHz PCI 33 MHz PCI 33 MHz PCI 33 MHz PCI 33 MHz
Intel (R) ICH6
66/33 Buffer
PCI 33 MHz PCI 33 MHz PCI 33 MHz PCI 33 MHz PCI 33 MHz
24 MHz Bit Clock
32.768 KHz
High Def Audio
PCI Slot PCI Slot PCI Slot PCI Slot
66 MHz
14.000 MHz
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PCI Slot PCI Slot
25 MHz Oscillator
66 MHz 66 MHz
Slot 3
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11
Electrical Characteristics
This chapter contains the MCH absolute maximum electrical ratings, power dissipation values, and DC characteristics.
11.1
Absolute Maximum Ratings
Table 11-1 lists the MCH's maximum environmental stress ratings. Functional operation at the absolute maximum and minimum is neither implied nor guaranteed. Functional operating parameters are listed in the DC tables.
Warning: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operating beyond the "operating conditions" is not recommended and extended exposure beyond "operating conditions" may affect reliability. Table 11-1. Absolute Maximum Ratings
Symbol Tstorage MCH Core VCC 1.5 V Core Supply Voltage with respect to VSS -0.3 1.65 V Parameter Storage Temperature Min -55 Max 150 Unit C Notes 1
Host Interface (800 MHz) VTT VCCA_HPLL 1.2 V System Bus Input Voltage with respect to VSS 1.5 V Host PLL Analog Supply Voltage with respect to VSS -0.3 -0.3 1.65 1.65 V V
DDR2 Interface (400 MHz / 533 MHz) VCCSM (DDR2) VCCA_SMPLL (DDR2) 1.8 V DDR2 System Memory Supply Voltage with Respect to VSS 1.5 V System Memory PLL Analog Supply Voltage with respect to VSS -0.3 -0.3 4.0 1.65 V V
PCI Express* / DMI Interface VCC_EXP VCCA_EXPPL L CMOS Interface VCC2 2.5 V CMOS Supply Voltage with respect to VSS -0.3 2.65 V 1.5 V PCI Express* and DMI Supply Voltage with respect to VSS 1.5 V PCI Express PLL Analog Supply Voltage with respect to VSS -0.3 -0.3 1.65 1.65 V V
NOTES: 1. Possible damage to the MCH may occur if the MCH temperature exceeds 150 C. Intel does not guarantee functionality for parts that have exceeded temperatures above 150 C due to specification violation.
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11.2
Power Characteristics
Symbol IVTT IVCC IVCC IVCC_EXP IVCC2 IVCCA_EXPPL
L
Table 11-2. Non-Memory Power Characteristics
Parameter 1.2 V System Bus Supply Bus Current 1.5 V Core Supply Current (Integrated) 1.5 V Core Supply Current (Discrete) 1.5 V PCI Express* and DMI Supply Current 2.5 V CMOS Supply Current 1.5 V PCI Express and DMI PLL Analog Supply Current 1.5 V Host PLL Supply Current Signal Names VTT VCC VCC VCC_EXP VCC2 VCCA_EXPPLL Min -- -- -- -- -- -- Typ -- -- -- -- -- -- Max 1.0 9.7 7.7 Unit A A A Notes 1, 4 2,3,4 2,3,4
1.4 2 45
A mA mA
IVCCA_HPLL
VCCA_HPLL
--
--
45
mA
NOTES: 1. Estimate is only for max current coming through the chipset's supply balls. 2. Rail includes PLL current. 3. Includes Worst case Leakage. 4. Calculated for highest frequencies.
Table 11-3. DDR2 Power Characteristics
Symbol IVCCSM (DDR2) ISUS_VCCSM (DDR2) ISMVREF (DDR2) ISUS_SMVRE
F
Parameter DDR2 System Memory Interface (1.8 V) Supply Current DDR2 System Memory Interface (1.8 V) Standby Supply Current DDR2 System Memory Interface Reference Voltage (0.90 V) Supply Current DDR2 System Memory Interface Reference Voltage (0.90 V) Standby Supply Current DDR2 System Memory Interface Resister Compensation Voltage (1.8 V) Supply Current DDR2 System Memory Interface Resister Compensation Voltage (1.8 V) Standby Supply Current System Memory PLL Analog (1.5 V) Supply Current
Min -- -- -- --
Max 4.7 25 10 10
Unit A mA A A
Notes
(DDR2) ITTRC (DDR2) ISUS_TTRC (DDR2) IVCCA_SMPL
L
-- --
32 0
mA A
--
--
--
(DDR2)
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11.3
Signal Groups
The signal description includes the type of buffer used for the particular signal: GTL+ DDR2 Open Drain GTL+ interface signal. Refer to the GTL+ I/O Specification for complete details. The MCH integrates most GTL+ termination resistors. DDR2 System Memory (1.8 V CMOS buffers)
PCI Express* PCI Express Interface Signals. These signals are compatible with the PCI Express Interface Specification 1.0a signaling environment AC specifications. The buffers are not 3.3V tolerant. Analog Ref HVCMOS SSTL-1.8 Analog signal interface. Voltage reference signal. 2.5 V tolerant high voltage CMOS buffers. 1.8 V tolerant stub series termination logic.
Table 11-4. Signal Groups
Signal Group Signal Type Signals Notes
Host Interface Signal Groups (a) GTL+ Input/Outputs HADS#, HBNR#, HBREQ0#, HDBSY#, HDRDY#, HDINV[3:0]#, HA[31:3]#, HADSTB[1:0]#, HD[63:0], HDSTBP[3:0]#, HDSTBN[3:0]#, HHIT#, HHITM#, HREQ[4:0]#, HLOCK# HBPRI#, HCPURST#, HDEFER#, HTRDY#, HRS[2:0]#, HDPWR#, HEDRDY# BSEL[2:0], HPCREQ# HVREF, HSWING HRCOMP, HSCOMP
(b) (c) (d)
GTL+ Common Clock Outputs GTL+ Asynchronous Input Analog Host I/F Ref & Comp. Signals
PCI Express* Interface Signal Groups (e) (f) (g) PCI Express* Input PCI Express Output Analog PCI Express I/F Compensation Signals PCI Express Interface: EXP_RXN(15:0), EXP_RXP(15:0), PCI Express Interface: EXP_TXN(15:0), EXP_TXP(15:0) EXP_COMP0 EXP_COMPI
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Signal Group
Signal Type
Signals
Notes
DDR2 Interface Signal Groups (k) (l) SSTL - 1.8 DDR2 CMOS I/O SSTL - 1.8 DDR2 CMOS Output SDQ_A[63:0]#, SDQ_B[63:0]#, SDQS_A[7:0], SDQS_A[7:0]#, SDQS_B[7:0]#, SDQS_B[7:0]# SDM_A[7:0], SDM_B[7:0], SMA[13:0], SMA_B[13:0] SBS_A[2:0], SBS_B[2:0] SRAS_A#, SRAS_B#, SCAS_A#, SCAS_B#, SWE_A#, SWE_B#, SODT_A[3:0], SODT_B[3:0], SCKE_A[3:0], SCKE_B[3:0], SCS_A[3:0]#, SCS_B[3:0]#, SCLK_A[5:0], SCLK_A[5:0]#, SCLK_B[5:0], SCLK_B[5:0]# SMVREF[1:0] (DDR2)
(m)
DDR2 Reference Voltage
Clocks, Reset, and Miscellaneous Signal Groups (n) (n1) (0) (p) HVCMOS Input Miscellaneous Inputs Low Voltage Diff. Clock Input HVCMOS I/O EXTTS# RSTIN#, PWROK HCLKN, HCLKP, DREFCLKP, DREFCLKN, GCLKP, GCLKN DDC_CLK, DDC_DATA
I/O Buffer Supply Voltages (q) (r) (t) 1.2 V System Bus Input Supply Voltage 1.5 V PCI Express Supply Voltages 1.8 V DDR2 Supply Voltage 1.5 V DDR2 PLL Analog Supply Voltage 1.5 V MCH Core Supply Voltage 2.5 V CMOS Supply Voltage PLL Analog Supply Voltages VTT VCC_EXP VCCSM (DDR2)
(v) (w) (x) (z)
VCCA_SMPLL (DDR2) VCC VCC2 VCCA_HPLL, VCCA_EXPPLL
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11.4
General DC Characteristics
Signal Group
Table 11-5. DC Characteristics
Symbol Parameter Min Nom Max Unit Notes3
I/O Buffer Supply Voltage (AC noise not included) VCCSM (DDR2) VCCA_SMPLL (DDR2) VCC_EXP VTT VCC VCC2 VCCA_HPLL, VCCA_EXPPLL (t) (v) (r) (q) (w) (x) (z) DDR2 I/O Supply Voltage DDR2 I/O PLL Analog Supply Voltage PCI Express* Supply Voltage System Bus Input Supply Voltage MCH Core Supply Voltage CMOS Supply Voltage Various PLL's Analog Supply Voltages 1.7 1.425 1.425 1.09 1.425 2.375 1.425 1.8 1.5 1.5 1.2 1.5 2.5 1.5 1.9 1.575 1.575 1.26 1.575 2.625 1.575 V V V V V V V
Reference Voltages HVREF (d) Host Address, Data, and Common Clock Signal Reference Voltage Host Compensation Reference Voltage DDR2 Reference Voltage 2/3 x VTT - 2% 1/4 x VTT -2% 0.49 x VCCSM (DDR2) 2/3 x VTT 2/3 x VTT + 2% 1/4 x VTT + 2% 0.51 x VCCSM (DDR2) V
HSWING SMVREF (DDR2)
(d) (m)
1/4 x VTT 0.50 x VCCSM (DDR2)
V V
Host Interface VIL_H VIH_H VOL_H VOH_H IOL_H ILEAK_H (a, c) (a, c) (a, b) (a, b) (a, b) (a, c) Host GTL+ Input Low Voltage Host GTL+ Input High Voltage Host GTL+ Output Low Voltage Host GTL+ Output High Voltage Host GTL+ Output Low Current Host GTL+ Input Leakage Current -0.10 (2/3 x VTT) + 0.1 -- VTT - 0.1 -- -- 0 VTT -- -- -- -- (2/3 x VTT) - 0.1 VTT + 0.1 (0.25 x VTT) + 0.1 VTT VTTmax / (1-0.25)Rttmin 20 V V V V mA A Rttmin = 54 VOL < Vpad < VTT
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Symbol CPAD CPCKG
Signal Group (a, c) (a, c)
Parameter Host GTL+ Input Capacitance Host GTL+ Input Capacitance (common clock)
Min 2 0.90
Nom -- --
Max 3.5 2.5
Unit pF pF
Notes3
DDR2 Interface VIL(DC) (DDR2) VIH(DC) (DDR2) (k) (k) DDR2 Input Low Voltage DDR2 Input High Voltage -- SMVREF (DDR2) + 0.125 -- SMVREF (DDR2) + 0.250 -- 1.5 -- 3.0 -- -- SMVREF (DDR2) - 0.125 -- V V
VIL(AC) (DDR2) VIH(AC) (DDR2)
(k) (k)
DDR2 Input Low Voltage DDR2 Input High Voltage
-- --
SMVREF (DDR2) - 0.250 --
V V
VOL (DDR2) VOH (DDR2) ILeak (DDR2) CI/O (DDR2)
(k, l) (k, l) (k) (k, l)
DDR2 Output Low Voltage DDR2 Output High Voltage Input Leakage Current DDR2 Input/Output Pin Capacitance
-- -- -- --
0.3
V V
1 1
10 6.0
A pF
1.5V PCI Express Interface Specification 1.0a VTX-DIFF P-P VTX_CM-ACp ZTX-DIFF-DC VRX-DIFF p-p VRX_CM-ACp (f) (f) (f) (e) (e) Differential Peak to Peak Output Voltage AC Peak Common Mode Output Voltage DC Differential TX Impedance Differential Peak to Peak Input Voltage AC peak Common Mode Input Voltage 0.400 -- 80 0.175 -- -- -- 100 -- -- 0.600 20 120 0.600 150 V mV Ohms V mV 3 2
Clocks, Reset, and Miscellaneous Signals VIL VIH ILEAK CIN VIL VIH (n) (n) (n) (n) (o) (o) Input Low Voltage Input High Voltage Input Leakage Current Input Capacitance Input Low Voltage Input High Voltage -- 2.0 -- 3.0 -- 0.660 -- -- -- -- 0 0.710 0.8 -- 10 6.0 -- 0.850 V V A pF V V
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Symbol VCROSS VOL VOH IOL IOH VIL VIH ILEAK CIN VIL VIH ILEAK
Signal Group (o) (p) (p) (p) (p) (p) (p) (p) (p) (n1) (n1) (n1)
Parameter Crossing Voltage Output Low Voltage (CMOS Outputs) Output High Voltage (CMOS Outputs) Output Low Current (CMOS Outputs) Output High Current (CMOS Outputs) Input Low Voltage Input High Voltage Crossing Voltage Input Capacitance Input Low Voltage Input High Voltage Crossing Voltage
Min 0.45 x (VIH - VIL) -- 2.1 -- -1 -- 1.4 -- 3.0 -- 2.0 --
Nom 0.5 x (VIH - VIL) -- -- -- -- --
Max 0.55 x (VIH - VIL) 0.4 -- 1 -- 1.1
Unit V V V mA mA V V
Notes3
@VOL_HI max @VOH_HI min
-- -- -- -- --
10 6.0 0.8 -- 100
A pF V V A 0 < Vin < VCC3_3
CIN
(n1)
Input Capacitance
4.690
--
5.370
pF
NOTES: 1. Determined with 2x MCH DDR2 Buffer Strength Settings into a 50 to 0.5xVCCSM (DDR2) test load. 2. Specified at the measurement point into a timing and voltage compliance test load as shown in Transmitter compliance eye diagram of the PCI Express Interface Specification 1.0a and measured over any 250 consecutive TX Uls. 3. Specified at the measurement point and measured over any 250 consecutive Uls. The test load shown in Receiver compliance eye diagram of the PCI Express Interface Specification 1.0a should be used as the RX device when taking measurements.
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Ballout and Package Information
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12
12.1
Ballout and Package Information
This chapter provides the ballout and package information.
Ballout
Figure 12-1 and Figure 12-2 show the 82925X MCH ballout as viewed from the top side of the package. Table 12-1 provides the MCH ballout sorted by signal name and Table 12-2 provides the MCH ballout sorted by ball number. Note: Balls that are listed as RSV are reserved. Board traces should be routed to these balls. Note: Balls that are listed as NC are No Connects.
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Figure 12-1. Intel 82925X MCH Ballout (Top View: Left Side)
(R)
1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR
2
3
4
5
VSS
6
7
8
9
10
VSS
11
GCLKP
GCLKN
12
VCCA_DPLLA
13
VCC2
VCCA_DPLLB
14
VCCA_EXPPLL
15
16
17
VCCA_HPLL
VCCA_SMPLL
18
VSS VSS VSS
NC VSS NC VSS VSS
EXP_TXP5
EXP_RXP4 EXP_RXN4
EXP_TXN3 EXP_TXP3 EXP_TXN1 EXP_TXP1
RSV RSV
VSS VSS VSS VSS VSS VSS
EXP_TXN4 EXP_TXP4 EXP_TXN2 EXP_TXP2 EXP_TXN0 EXP_TXP0
VSS
VSS RSV VSS
MTYPE
VSS VSS VSS VSS
EXP_TXP6
VSS
VSS RSV RSV RSV RSV
NC VSS VSS
BSEL2
EXP_TXN5
EXP_RXP5
VSS VSS VSS VSS VSS VSS RSV RSV RSV VSS VSS VSS
EXP_RXN3
VSS VSS
EXP_TXP7
VSS VSS VSS VSS VSS VSS VSS VSS
EXP_RXN5
VSS VSS
EXP_RXN2
VSS VSS
EXP_RXP0
BSEL1
NC VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
EXP_TXN6
VSS VSS VSS
EXP_RXN6 EXP_RXP6
EXP_RXP3
EXP_RXP2
EXP_RXN0
NC RSV RSV RSV VSS HD47 VSS NC VSS RSV NC NC HD46
HD44 HD43
EXP_TXN7
EXP_TXP8
VSS VSS VSS VSS VSS NC VSS RSV VSS RSV VSS HD45
EXP_RXN7 EXP_RXP7
EXP_TXP9
EXP_TXN8
VSS VSS VSS
EXP_RXN8 EXP_RXP8
VSS VSS
EXP_RXN1
BSEL0
EXP_TXN9
EXP_TXP10
VSS VSS VSS VSS
EXP_RXN9 EXP_RXP9
EXP_RXP1
NC RSV RSV VSS VSS VSS VSS
EXTTS#
EXP_TXP11
EXP_TXN10
VSS VSS VSS
EXP_RXN10
VSS VSS VSS NC RSV VSS RSV VSS VSS VSS VSS
EXP_TXN11
EXP_TXP12
EXP_RXP10
VSS VSS VSS VCC VSS NC VSS RSV VSS VSS VSS VSS
EXP_RXN12
EXP_TXP13
EXP_TXN12
VSS VSS VSS
EXP_RXN13
EXP_RXP12
DREFCLKN
DREFCLKP
ICH_SYNC#
RSV RSV VSS HD42
EXP_TXN13
EXP_TXP14
EXP_RXP13
VSS VSS VSS VSS VSS NC VCC VCC VCC VCC VSS VCC
EXP_RXP14
EXP_RXN14
EXP_TXP15
EXP_TXN14
VSS VSS VSS
EXP_RXN15
EXP_RXP11
VSS NC VCC VCC VCC VSS VCC VSS VSS NC VCC VCC VCC VCC VSS VCC VSS NC VCC VCC VSS VCC VSS VCC VSS NC VCC VCC VCC VSS VCC VSS VSS NC VCC VCC VSS VCC VSS VCC VSS NC VCC VCC VCC VCC VCC VSS
EXP_TXN15
DMI_TXP0
EXP_RXP15
VSS VSS VSS
DMI_RXN1 DMI_RXP1
EXP_RXN11
DMI_TXP1
DMI_TXN0
VSS VSS VSS VSS
DMI_RXP0 DMI_RXN0
VSS VSS NC VCC VCC VCC VCC VCC VSS
DMI_RXN3
DMI_TXN1
DMI_TXP2
VSS VSS VSS
DMI_RXP2 DMI_RXN2
VSS VSS
DMI_TXN2
DMI_TXP3
VSS
VSS
DMI_RXP3
VCC_EXP VCC_EXP VCC_EXP VCC_EXP DMI_TXN3 VCC_EXP VCC_EXP VCC_EXP VCC_EXP
EXP_COMPI
VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP
EXP_COMPO
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC VCC VCC VSS VCC VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC NC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC RSV RSV RSV RSV RSV RSV RSV VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VSS
SDQ_A5 SDQ_A4 SDQ_A0
SDQ_B20
VSS
SDQ_B17 SDQ_B29
VSS
SDQ_A29 SDQ_B24
VSS VSS
SOCOMP1
VSS VSS
SVREF0 SVREF1
VSS
SMSLEWIN1
SMSLEWOUT1
SDQ_B4
VSS
SDQ_B21 SDQ_B19 SDQ_A28 RSV_TP0 SDQ_A24
NC VSS VSS VSS
VSS VSS VSS
SDM_A1
SDM_A0 SDQ_A1
SOCOMP0
RSTIN#
PWROK
VSS
SRCOMP1
VSS
SDQ_B5 SDQ_B11 SDQ_B16 SDQ_B18 SDQ_B28 SDQ_A25 SDM_A3
SDQS_A0 SDQS_A0# SDQ_A6 SRCOMP0
VSS NC NC VSS VSS VSS
VSS
SDQS_B0#
SDQ_B1 SDQ_B0
SDM_B0
VSS VSS
SDM_B2 SDQS_B2
SDQS_B2#
VSS VSS
SDQS_A3#
SDQ_A7 SDQ_A2 SDQ_B12
SDQ_B7 SDQS_B0
VSS VSS
SCLK_B1
VSS VSS
RSV_TP1 SDQS_A3 SDQ_A27
SDQ_A12 SDQ_A3 SDQ_A13
VSS VSS
SDQ_B9
SDQ_B13 SDQ_B3 SDQ_B2 SDQ_B6
VSS VSS
SCLK_B4 SDQ_B8
SCLK_B1# SMSLEWIN0
VSS NC VSS VSS
SDQ_B22 RSV_TP3 SDQ_A30
SDQ_A31 SCB_B1
SDQ_A8 SDQ_A9
SDQS_A1# SDQS_A1
SDM_B1
SDQ_A17
VSS
SMSLEWOUT0
VSS
SCB_B5
SDQS_B1# SDQ_B14 SDQ_A19 SDQ_B10 SCLK_B4#
VSS
VCCSM
VSS
SDQ_B23 RSV_TP2
VSS
SDQ_A26 SDQ_B26
SCLK_A1 SCLK_A1#
VSS
SDQS_B1
SDQ_A22 SDQ_A23 SDQ_A18
VCCSM VCCSM
NC
VCCSM VCCSM
NC
VCCSM VCCSM
NC
VSS NC NC
SCLK_A4 SCLK_A4# SDQ_A10 SDQ_A21 SDQ_B15 SDQS_A2# SCKE_B3
SBS_B2 SMA_B12 SMA_B5
SMA_B4 SMA_B2 SMA_B0 SBS_B1 SRAS_B# SCKE_A2
SDQ_A14 SDQ_A15 SDQ_A11 SDQ_A16 SDM_A2 SDQS_A2
VCCSM SCKE_B1 SMA_B11 SMA_B9 VCCSM SMA_B6 SMA_B3 SMA_B10 VCCSM SWE_B# SCAS_B#
NC VSS
SDQ_A20
VSS
VCCSM SCKE_B2 SCKE_B0 VCCSM SMA_B7 SMA_B8
VSS
VCCSM SMA_B1 SBS_B0
VSS
VCCSM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Intel 82925X MCH Datasheet
(R)
195
Ballout and Package Information
R
Figure 12-2. Intel 82925X MCH Ballout (Top View: Right Side)
(R)
19 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR
20
21
22
23
HSWING
HRCOMP
24
HVREF
25
HD48
26
HDINV3#
27
HD54
28
VSS
29
HDSTBP3#
30
31
32
33
34
35
NC NC
VTT VTT VTT VTT VTT VTT VTT VTT
VSS HD61 HD57 HD55 VSS HD53
HD17 HD50 HD14
VSS NC
VSS HD63
HD51 HD52 HD15 HD13 HD11
VTT VTT VTT VTT VSS VTT VTT VTT VTT VSS
HSCOMP
HD58 HD59 HD49 HD56
HDSTBN3#
HD9 HD12 VSS
VSS VSS HD60 VSS HD18 VSS VSS VSS HD10 HD8
HBPRI#
HPCREQ#
VTT VTT VTT VTT VSS HD62 HD25 VSS HD24 HD16 VSS
HDSTBN2#
HREQ1#
HDSTBP0#
HDINV0# HDSTBN0#
VTT VTT VTT VSS NC VSS
HCPURST#
HDSTBN1#
HD23 HD22
VSS VSS
HD20 HA6#
HREQ4# HREQ3# HREQ2#
HADSTB0#
VSS
HREQ0#
HD6 VSS
VSS VSS VTT VTT VSS
HD41 HD40
HDSTBP2#
HD26
VSS VSS VSS
HDSTBP1#
HA7# HD7 HD5 HD3
VSS VTT HD37 VSS VSS
VSS HD19 HA3# VSS
HD21 HA13# HA5#
HA14#
VSS HD1 VSS HD4
HRS2#
VSS HD35 HD32 VSS HD33 HD27
HDINV1#
VSS
HD0 HD2
HA15# HRS0#
HLOCK#
HDEFER#
HDINV2#
VSS HD39 HD34 HD31 VSS HD28 VSS
HA18# HA20# HA19# HA22#
VSS HA4# HA8# VSS VSS
HA12# HA16#
VSS
HDBSY#
NC VSS VSS VSS HD30 VSS HD29
HD38
VSS VSS
HADSTB1#
HA9# VSS HA11# VSS
HHIT#
VSS HD36
HCLKN HCLKP
VSS VSS NC VSS NC VSS
VSS
HA23#
HA10# HADS#
HDRDY#
VSS
HA26#
HEDRDY#
HBNR#
VSS VCC VCC NC
NC
VSS
HA24#
VSS
HA21#
VSS
HTRDY# HHITM#
VCC VSS VCC VCC NC
VSS
VSS NC VSS VSS VSS
SDQS_A8#
HRS1#
VSS RSV
SDQ_A63
VSS VCC VSS VCC VCC NC VSS VSS VSS VCC VCC VCC VSS VCC VCC VSS VSS VCC VSS VCC VSS VCC VSS VSS VCC VSS VCC VSS VCC VSS VCC VCC VCC VSS VCC VCC VSS VCC VCC VCC VCC VCC VCC VSS RSV RSV RSV RSV NC VSS VSS NC VSS
SDQ_B25 SDM_B3
HA25# HA17#
SCB_A4 SCB_A5 SDQ_A58 HBREQ0# SDQ_A59
HA30# HA27#
SDQ_B63
VSS
HA29#
HA31#
HA28#
VSS
SDQ_A62
VSS
VSS
VSS
VSS VSS VSS
SDM_A7 SDQS_A7
SDQS_A7#
VCC VSS VCC VSS VCC VCC VSS VSS VSS
SDQ_B62 SDQS_B7
SDQ_B58 SDQ_B59 SDQS_A8 SCB_A1 SCB_A0 SDQ_A57 SDQ_A56
VSS
VSS
SDQS_B7#
SDQ_B57
VSS
SCB_A6
SDM_B7
SDQ_A61 SDQ_A51 SDQ_A60
SDQ_B60
VSS
VSS
VSS VSS
SDQ_A50
VSS
SDQ_A55
VSS VCC VCC VCC VCC VCC VSS VSS VSS
SDQ_B51 SDQ_B55
SDQ_B56 SDQ_B61 SCB_A3 SCB_A2 SDQ_A54 SDM_A6 SDQS_A6 SDQS_A6#
VSS
SDQ_B54
SCB_A7
VSS
SDQS_B6#
SDQS_B6
VSS RSV RSV VSS
SCLK_A2
VSS
SCLK_A5
NC VSS
SDQ_B50
VSS
VSS
VSS VSS
SDQ_A48
SCLK_A2# SCLK_A5#
SDQ_B37 SDM_B6
VSS VSS
SCLK_B2#
SDQ_A35 SCLK_B5# SCLK_B5
NC NC
SDQ_B43
VSS
SDQ_A49
VSS VSS VSS VSS VSS NC VSS VSS
SDQ_B31
SCLK_B2 SDQ_B49
VSS
SDQ_B53
SDQ_B52
SDQ_A43 SDQ_A53 SDQ_A52
NC VSS
SDQ_B30
SDQS_B3#
SDQ_B36 SDQ_B32 SDM_B4
SCLK_B0# SDQ_B33
VSS VSS
SDQ_B48 SDQ_A39
VSS NC VSS
VSS VSS
SDQ_A42 SDQ_A47
VSS
SDQS_B3
NC
SDQS_B4
SDQS_B4# SDQ_A38 SDQ_B47
SDQ_B46 SDQ_B42 SDQ_A46 SDQS_A5# SDM_A5 SDQS_A5
VSS
SCB_B0
VSS VSS
SCLK_B0
NC
SDQ_A34 SDQS_B5
SDQS_B5#
SDM_B5
SDQ_B41
VSS VSS VSS VSS
SDQ_A40 SDQ_A41
VSS
SDQ_B27
SDQS_B8#
SCB_B2 SCB_B3 SDQ_B39 SDQ_B35
VSS NC
SDQS_A4# SDQ_B44
VSS VSS
SDM_A4 SDQ_A45
VSS
VCCSM
VSS
SDQS_B8 SCLK_B3#
VSS NC VSS VSS VSS NC
SDQ_B38 SDQ_B34
SDQS_A4 SCLK_A0 SDQ_A32
SDQ_A33 SDQ_B40 SDQ_B45 SDQ_A44
VSS
SCB_B4 SCB_B6 SCB_B7 SCLK_B3
SCLK_A0# SCLK_A3# SDQ_A36 SDQ_A37
SODT_B3 SODT_B1 SODT_B2
VCCSM VCCSM
NC
VCCSM VCCSM
VCCSM VCCSM VCCSM
VSS
VCCSM SCLK_A3
VSS
VCCSM SCS_B1# SCS_A3#
SCKE_A1 SMA_A12 SMA_A7 SMA_A5 SMA_A8 SCKE_A0
SMA_A2 SMA_A0 SBS_A0 SWE_A# SODT_A2 SMA_A13 SCS_A1# SODT_A3 SCS_B2# SODT_B0 VCCSM
SODT_A0 SCS_A3# SODT_A1 SCS_B0# SCS_B3#
VCCSM SMA_A11 SMA_A9 SMA_A4 VCCSM SMA_A1 SMA_A10 SRAS_A# VCCSM SCAS_A#
NC NC
SCKE_A3 SBS_A2
VSS
VCCSM SMA_A6 SMA_A3
VSS
VCCSM SBS_A1 SCS_A2# SCS_A0#
VSS
VCCSM
VCCSM
NC
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
196
Intel 82925X MCH Datasheet
(R)
Ballout and Package Information
R
Table 12-1. MCH Ballout Sorted By Signal Name Signal Name BSEL0 BSEL1 BSEL2 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 DREFCLKN DREFCLKP EXP_COMPI EXP_COMPO EXP_RXN0 EXP_RXN1 EXP_RXN10 EXP_RXN11 EXP_RXN12 EXP_RXN13 EXP_RXN14 EXP_RXN15 EXP_RXN2 EXP_RXN3 EXP_RXN4 EXP_RXN5 EXP_RXN6 EXP_RXN7 Ball # H16 E15 D17 U6 T8 V8 U10 U5 T9 V7 V10 T3 U1 V3 W5 R3 T1 U3 V5 M12 M13 W10 Y10 F11 H11 L5 R10 M7 N5 P8 R5 E9 E7 B4 E5 G5 H7
Table 12-1. MCH Ballout Sorted By Signal Name Signal Name EXP_RXN8 EXP_RXN9 EXP_RXP0 EXP_RXP1 EXP_RXP10 EXP_RXP11 EXP_RXP12 EXP_RXP13 EXP_RXP14 EXP_RXP15 EXP_RXP2 EXP_RXP3 EXP_RXP4 EXP_RXP5 EXP_RXP6 EXP_RXP7 EXP_RXP8 EXP_RXP9 EXP_TXN0 EXP_TXN1 EXP_TXN10 EXP_TXN11 EXP_TXN12 EXP_TXN13 EXP_TXN14 EXP_TXN15 EXP_TXN2 EXP_TXN3 EXP_TXN4 EXP_TXN5 EXP_TXN6 EXP_TXN7 EXP_TXN8 EXP_TXN9 EXP_TXP0 EXP_TXP1 EXP_TXP10 Ball # J5 K7 E11 J11 L6 P10 M8 N6 P7 R6 F9 F7 B3 D5 G6 H8 J6 K8 C9 A8 K3 L1 M3 N1 P3 R1 C7 A6 C5 D2 F3 G1 H3 J1 C10 A9 J3
Table 12-1. MCH Ballout Sorted By Signal Name Signal Name EXP_TXP11 EXP_TXP12 EXP_TXP13 EXP_TXP14 EXP_TXP15 EXP_TXP2 EXP_TXP3 EXP_TXP4 EXP_TXP5 EXP_TXP6 EXP_TXP7 EXP_TXP8 EXP_TXP9 EXTTS# GCLKN GCLKP HA3# HA4# HA5# HA6# HA7# HA8# HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# Ball # K1 L3 M1 N3 P1 C8 A7 C6 C2 E3 F1 G3 H1 K16 B11 A11 H29 K29 J29 G30 G32 K30 L29 M30 L31 L28 J28 K27 K33 M28 R29 L26 N26 M26 N31 P26 N29
Intel 82925X MCH Datasheet
(R)
197
Ballout and Package Information
R
Table 12-1. MCH Ballout Sorted By Signal Name Signal Name HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31# HADS# HADSTB0# HADSTB1# HBNR# HBPRI# HBREQ0# HCLKN HCLKP HCPURST# HD00 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9 HD10 HD11 HD12 HD13 HD14 HD15 HD16 HD17 HD18 HD19 HD20 Ball # P28 R28 N33 T27 T31 U28 T26 T29 M31 J31 N27 M35 E30 R33 M22 M23 G24 J33 H33 J34 G35 H35 G34 F34 G33 D34 C33 D33 B34 C34 B33 C32 B32 E28 C30 D29 H28 G29
Table 12-1. MCH Ballout Sorted By Signal Name Signal Name HD21 HD22 HD23 HD24 HD25 HD26 HD27 HD28 HD29 HD30 HD31 HD32 HD33 HD34 HD35 HD36 HD37 HD38 HD39 HD40 HD41 HD42 HD43 HD44 HD45 HD46 HD47 HD48 HD49 HD50 HD51 HD52 HD53 HD54 HD55 HD56 HD57 HD58 Ball # J27 F28 F27 E27 E25 G25 J25 K25 L25 L23 K23 J22 J24 K22 J21 M21 H23 M19 K21 H20 H19 M18 K18 K17 G18 H18 F17 A25 C27 C31 B30 B31 A31 B27 A29 C28 A28 C25
Table 12-1. MCH Ballout Sorted By Signal Name Signal Name HD59 HD60 HD61 HD62 HD63 HDBSY# HDEFER# HDINV0# HDINV1# HDINV2# HDINV3# HDRDY# HDSTBN0# HDSTBN1# HDSTBN2# HDSTBN3# HDSTBP0# HDSTBP1# HDSTBP2# HDSTBP3# HEDRDY# HHIT# HHITM# HLOCK# HPCREQ# HRCOMP HREQ0# HREQ1# HREQ2# HREQ3# HREQ4# HRS0# HRS1# HRS2# HSCOMP HSWING HTRDY# HVREF Ball # C26 D27 A27 E24 B25 L35 J35 E34 J26 K19 B26 M32 E35 F26 F19 C29 E33 H26 J19 B29 P33 L34 N35 L33 E31 B23 F33 E32 H31 G31 F31 K34 P34 J32 D24 A23 N34 A24
198
Intel 82925X MCH Datasheet
(R)
Ballout and Package Information
R
Table 12-1. MCH Ballout Sorted By Signal Name Signal Name ICH_SYNC# MTYPE NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Ball # M14 C15 A34 A35 AA12 AB12 AC23 AC24 AD21 AD30 AE18 AE30 AF19 AF22 AG25 AG29 AG6 AH24 AH5 AJ14 AK24 AL27 AM12 AM15 AM18 AM21 AM24 AP1 AP35 AR1 AR2 AR34 AR35 B1 B35 C16 E16 F12
Table 12-1. MCH Ballout Sorted By Signal Name Signal Name NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC PWROK RSTIN# RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV Ball # F24 G12 H12 H15 H17 J12 K12 L12 L19 N12 N22 N23 N24 P12 P23 P24 P30 R12 R24 T12 U12 V12 W12 Y12 A2 AG7 AF7 H14 J14 M15 L14 D14 E14 E12 F14 G14 A15 A16
Table 12-1. MCH Ballout Sorted By Signal Name Signal Name RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV_TP0 RSV_TP1 RSV_TP2 RSV_TP3 SBS_A0 SBS_A1 SBS_A2 SBS_B0 SBS_B1 SBS_B2 SCAS_A# SCAS_B# Ball # AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 B15 C14 F15 G16 J13 K13 K15 M16 R35 D13 E13 F13 AB33 AD32 D12 AE16 AH15 AL15 AK15 AN27 AR27 AR20 AR16 AN16 AN9 AP29 AP18
Intel 82925X MCH Datasheet
(R)
199
Ballout and Package Information
R
Table 12-1. MCH Ballout Sorted By Signal Name Signal Name SCB_A0 SCB_A1 SCB_A2 SCB_A3 SCB_A4 SCB_A5 SCB_A6 SCB_A7 SCB_B0 SCB_B1 SCB_B2 SCB_B3 SCB_B4 SCB_B5 SCB_B6 SCB_B7 SCKE_A0 SCKE_A1 SCKE_A2 SCKE_A3 SCKE_B0 SCKE_B1 SCKE_B2 SCKE_B3 SCLK_A0 SCLK_A0# SCLK_A1 SCLK_A1# SCLK_A2 SCLK_A2# SCLK_A3 SCLK_A3# SCLK_A4 SCLK_A4# SCLK_A5 SCLK_A5# SCLK_B0 SCLK_B0# Ball # V32 V31 AA31 AA30 R30 R31 Y30 AB29 AJ20 AJ18 AJ23 AJ24 AL20 AK18 AL21 AL22 AP19 AN19 AN18 AR19 AR9 AP9 AR8 AN8 AL29 AM30 AN2 AN3 AC34 AC35 AL28 AK28 AM3 AM2 AC33 AB34 AH23 AG23
Table 12-1. MCH Ballout Sorted By Signal Name Signal Name SCLK_B1 SCLK_B1# SCLK_B2 SCLK_B2# SCLK_B3 SCLK_B3# SCLK_B4 SCLK_B4# SCLK_B5 SCLK_B5# SCS_A0# SCS_A1# SCS_A2# SCS_A3# SCS_B0# SCS_B1# SCS_B2# SCS_B3# SDM_A0 SDM_A1 SDM_A2 SDM_A3 SDM_A4 SDM_A5 SDM_A6 SDM_A7 SDM_B0 SDM_B1 SDM_B2 SDM_B3 SDM_B4 SDM_B5 SDM_B6 SDM_B7 SDQ_A00 SDQ_A01 SDQ_A02 SDQ_A03 Ball # AK9 AL9 AE26 AE25 AL23 AK22 AJ11 AL11 AD28 AD29 AR29 AN31 AR28 AP31 AP33 AM33 AN33 AP34 AF2 AL1 AP6 AF17 AJ33 AG34 AA33 U33 AH10 AK5 AH12 AE20 AF25 AH31 AD24 W31 AE3 AF3 AH3 AJ2
Table 12-1. MCH Ballout Sorted By Signal Name Signal Name SDQ_A04 SDQ_A05 SDQ_A06 SDQ_A07 SDQ_A08 SDQ_A09 SDQ_A10 SDQ_A11 SDQ_A12 SDQ_A13 SDQ_A14 SDQ_A15 SDQ_A16 SDQ_A17 SDQ_A18 SDQ_A19 SDQ_A20 SDQ_A21 SDQ_A22 SDQ_A23 SDQ_A24 SDQ_A25 SDQ_A26 SDQ_A27 SDQ_A28 SDQ_A29 SDQ_A30 SDQ_A31 SDQ_A32 SDQ_A33 SDQ_A34 SDQ_A35 SDQ_A36 SDQ_A37 SDQ_A38 SDQ_A39 SDQ_A40 SDQ_A41 Ball # AE2 AE1 AG3 AH2 AK2 AK3 AN4 AP4 AJ1 AJ3 AP2 AP3 AP5 AK7 AM9 AL7 AR5 AN5 AM7 AM8 AE17 AF16 AL17 AH17 AE15 AD17 AK16 AJ17 AK29 AK31 AH27 AD27 AL30 AL31 AG27 AF28 AH34 AH35
200
Intel 82925X MCH Datasheet
(R)
Ballout and Package Information
R
Table 12-1. MCH Ballout Sorted By Signal Name Signal Name SDQ_A42 SDQ_A43 SDQ_A44 SDQ_A45 SDQ_A46 SDQ_A47 SDQ_A48 SDQ_A49 SDQ_A50 SDQ_A51 SDQ_A52 SDQ_A53 SDQ_A54 SDQ_A55 SDQ_A56 SDQ_A57 SDQ_A58 SDQ_A59 SDQ_A60 SDQ_A61 SDQ_A62 SDQ_A63 SDQ_B00 SDQ_B01 SDQ_B02 SDQ_B03 SDQ_B04 SDQ_B05 SDQ_B06 SDQ_B07 SDQ_B08 SDQ_B09 SDQ_B10 SDQ_B11 SDQ_B12 SDQ_B13 SDQ_B14 SDQ_B15 Ball # AF33 AE33 AK34 AJ34 AG32 AF34 AD31 AD35 Y33 W34 AE35 AE34 AA32 Y35 V34 V33 R32 R34 W35 W33 T33 T35 AG11 AG10 AJ7 AJ6 AE11 AF11 AJ8 AH7 AK10 AL4 AL8 AF12 AH4 AJ5 AL6 AN6
Table 12-1. MCH Ballout Sorted By Signal Name Signal Name SDQ_B16 SDQ_B17 SDQ_B18 SDQ_B19 SDQ_B20 SDQ_B21 SDQ_B22 SDQ_B23 SDQ_B24 SDQ_B25 SDQ_B26 SDQ_B27 SDQ_B28 SDQ_B29 SDQ_B30 SDQ_B31 SDQ_B32 SDQ_B33 SDQ_B34 SDQ_B35 SDQ_B36 SDQ_B37 SDQ_B38 SDQ_B39 SDQ_B40 SDQ_B41 SDQ_B42 SDQ_B43 SDQ_B44 SDQ_B45 SDQ_B46 SDQ_B47 SDQ_B48 SDQ_B49 SDQ_B50 SDQ_B51 SDQ_B52 SDQ_B53 Ball # AF13 AD14 AF14 AE14 AD12 AE13 AK13 AL14 AD18 AE19 AL18 AK19 AF15 AD15 AH19 AH21 AF24 AG24 AL26 AJ26 AF23 AD23 AL25 AJ25 AK32 AJ31 AG31 AF30 AJ29 AK33 AG30 AG28 AF27 AE27 AC26 AB26 AE31 AE29
Table 12-1. MCH Ballout Sorted By Signal Name Signal Name SDQ_B54 SDQ_B55 SDQ_B56 SDQ_B57 SDQ_B58 SDQ_B59 SDQ_B60 SDQ_B61 SDQ_B62 SDQ_B63 SDQS_A0 SDQS_A0# SDQS_A1 SDQS_A1# SDQS_A2 SDQS_A2# SDQS_A3 SDQS_A3# SDQS_A4 SDQS_A4# SDQS_A5 SDQS_A5# SDQS_A6 SDQS_A6# SDQS_A7 SDQS_A7# SDQS_A8 SDQS_A8# SDQS_B0 SDQS_B0# SDQS_B1 SDQS_B1# SDQS_B2 SDQS_B2# SDQS_B3 SDQS_B3# SDQS_B4 SDQS_B4# Ball # AC28 AB27 AA28 W29 V28 V29 Y26 AA29 W26 U26 AG1 AG2 AL3 AL2 AP7 AN7 AH16 AG17 AK27 AJ28 AG35 AG33 AA34 AA35 U34 U35 V30 U30 AH8 AH9 AM5 AL5 AH13 AG14 AG20 AF20 AH25 AG26
Intel 82925X MCH Datasheet
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Table 12-1. MCH Ballout Sorted By Signal Name Signal Name SDQS_B5 SDQS_B5# SDQS_B6 SDQS_B6# SDQS_B7 SDQS_B7# SDQS_B8 SDQS_B8# SMA_A0 SMA_A1 SMA_A2 SMA_A3 SMA_A4 SMA_A5 SMA_A6 SMA_A7 SMA_A8 SMA_A9 SMA_A10 SMA_A11 SMA_A12 SMA_A13 SMA_B0 SMA_B1 SMA_B2 SMA_B3 SMA_B4 SMA_B5 SMA_B6 SMA_B7 SMA_B8 SMA_B9 SMA_B10 SMA_B11 SMA_B12 SMA_B13 SMSLEWIN0 SMSLEWIN1 Ball # AH28 AH30 AB31 AC30 W27 Y28 AK21 AJ21 AN26 AP25 AN25 AR24 AP23 AN22 AR23 AN21 AN23 AP22 AP26 AP21 AN20 AN30 AN15 AR15 AN14 AP14 AN13 AN11 AP13 AR11 AR12 AP11 AP15 AP10 AN10 AM34 AJ12 AF9
Table 12-1. MCH Ballout Sorted By Signal Name Signal Name SMSLEWOUT0 SMSLEWOUT1 SOCOMP0 SOCOMP1 SODT_A0 SODT_A1 SODT_A2 SODT_A3 SODT_B0 SODT_B1 SODT_B2 SODT_B3 SRAS_A# SRAS_B# SRCOMP0 SRCOMP1 SVREF0 SVREF1 SWE_A# SWE_B# VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Ball # AK12 AE10 AF5 AE5 AP30 AP32 AN29 AN32 AN34 AL34 AL35 AL33 AP27 AN17 AG4 AG8 AE7 AE8 AN28 AP17 R16 R18 R20 R22 R23 T13 T14 T15 T16 T17 T19 T20 T21 T23 T24 U13 U14 U16
Table 12-1. MCH Ballout Sorted By Signal Name Signal Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Ball # U18 U20 U22 U24 V13 V14 V15 V17 V19 V21 V23 V24 W13 W14 W16 W18 W20 W22 W24 Y13 Y14 AA13 AA14 AA16 AA18 AA20 AA21 AA22 AA23 AA24 AB1 AB10 AB11 AB13 AB14 AB15 AB16 AB17
202
Intel 82925X MCH Datasheet
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Table 12-1. MCH Ballout Sorted By Signal Name Signal Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Ball # AB18 AB19 AB2 AB20 AB21 AB22 AB23 AB24 AB3 AB4 AB5 AB6 AB7 AB8 AB9 Y15 Y16 Y17 Y19 Y20 Y21 Y23 Y24 AC1 AC10 AC11 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AD1 AD10 AD2 AD3
Table 12-1. MCH Ballout Sorted By Signal Name Signal Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP Ball # AD4 AD5 AD6 AD7 AD8 AD9 L10 N13 N14 N15 N16 N18 N20 N21 P13 P14 P15 P17 P19 P21 P22 R13 R14 R15 W1 W2 W3 W4 W6 W7 W8 W9 Y1 Y2 Y3 Y4 Y5 Y6
Table 12-1. MCH Ballout Sorted By Signal Name Signal Name VCC_EXP VCC_EXP VCC_EXP VCC2 VCCA_DPLLA VCCA_DPLLB VCCA_EXPPLL VCCA_HPLL VCCA_SMPLL VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM Ball # Y7 Y8 Y9 A13 A12 B13 A14 A17 B17 AK35 AL12 AM10 AM11 AM13 AM14 AM16 AM17 AM19 AM20 AM22 AM23 AM26 AM27 AM29 AM32 AN35 AP12 AP16 AP20 AP24 AP28 AP8 AR10 AR14 AR18 AR22 AR26 AR31
Intel 82925X MCH Datasheet
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Table 12-1. MCH Ballout Sorted By Signal Name Signal Name VCCSM VCCSM VCCSM VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # AR33 AR7 AM25 AA26 AA27 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AB25 AB28 AB30 AB32 AB35 AC25 AC27 AC29 AC31 AC32 AD11 AD13 AD16 AD19 AD20 AD22 AD25 AD26 AD34 AE12 AE21 AE22 AE23 AE24 AE28 AE32
Table 12-1. MCH Ballout Sorted By Signal Name Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # AE4 AE6 AE9 AF1 B18 B2 B24 B28 B5 B6 B7 B8 B9 C1 C11 C13 C17 C18 C23 C3 C35 C4 D10 D11 D15 D16 D18 D23 D25 D26 D28 D3 D30 D31 D32 D4 D6 D7
Table 12-1. MCH Ballout Sorted By Signal Name Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # D8 D9 E1 E10 E17 K6 K9 L11 L13 L15 L16 L17 L18 L2 L20 L21 L22 L24 L27 L30 L32 L4 L7 L8 L9 M10 M11 M17 M2 M20 M24 M25 M27 M29 M34 M4 M5 M6
204
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Table 12-1. MCH Ballout Sorted By Signal Name Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # M9 N10 N11 N17 N19 N2 W19 W21 W23 W25 W28 W30 W32 Y11 Y18 Y22 Y25 Y27 Y29 Y31 AF10 AF18 AF21 AF26 AF29 AF31 AF32 AF35 AF4 AF6 AF8 AG12 AG13 AG15 AG16 AG18 AG19 AG21
Table 12-1. MCH Ballout Sorted By Signal Name Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # AG22 AG5 AG9 AH1 AH11 AH14 AH18 AH20 AH22 AH26 AH29 AH32 AH33 AH6 AJ10 AJ13 AJ15 AJ16 AJ19 AJ22 AJ27 E18 E2 E23 E26 E29 E4 E6 E8 F10 F16 F18 F2 F23 F25 F29 F30 F32
Table 12-1. MCH Ballout Sorted By Signal Name Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # F35 F4 F5 F6 F8 G10 G11 G13 G15 G17 G19 G2 G20 G23 G26 G27 G28 G4 G7 G8 G9 H10 N25 N28 N30 N32 N4 N7 N8 N9 P11 P16 P18 P2 P20 P25 P27 P29
Intel 82925X MCH Datasheet
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Table 12-1. MCH Ballout Sorted By Signal Name Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # P31 P32 P35 P4 P5 P6 P9 R11 R17 R19 R2 R21 R25 R26 R27 R4 R7 R8 R9 T10 T11 T18 T2 Y32 Y34 A10 A18 A26 A3 A30 A33 A5 AA1 AA10 AA11 AA15 AA17 AA19
Table 12-1. MCH Ballout Sorted By Signal Name Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # AA2 AA25 AJ30 AJ32 AJ35 AJ4 AJ9 AK1 AK11 AK14 AK17 AK20 AK23 AK25 AK26 AK30 AK4 AK6 AK8 AL10 AL13 AL16 AL19 AL24 AL32 AM28 AM31 AM4 AM6 AN1 AR13 AR17 AR21 AR25 AR3 AR30 AR6 B10
Table 12-1. MCH Ballout Sorted By Signal Name Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # B12 B14 B16 H13 H2 H21 H24 H25 H27 H30 H32 H34 H4 H5 H6 H9 J10 J15 J16 J17 J18 J2 J20 J23 J30 J4 J7 J8 J9 K10 K11 K14 K2 K20 K24 K26 K28 K31
206
Intel 82925X MCH Datasheet
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Table 12-1. MCH Ballout Sorted By Signal Name Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # K32 K35 K4 K5 T22 T25 T28 T30 T32 T34 T4 T5 T6 T7 U11 U15 U17 U19 U2 U21 U23 U25 U27 U29 U31 U32 U4 U7 U8 U9 V1 V11 V16 V18 V2 V20 V22 V25
Table 12-1. MCH Ballout Sorted By Signal Name Signal Name VSS VSS VSS VSS VSS VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT Ball # V26 V27 V35 V4 V6 A19 A20 A21 A22 B19 B20 B21 B22 C19 C20 C21 C22 D19 D20 D21 D22 E19 E20 E21 E22 F20 F21 F22 G21 G22 H22
Intel 82925X MCH Datasheet
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Table 12-2. MCH Ballout Sorted By Ball Number Ball # A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 -- NC VSS -- VSS EXP_TXN3 EXP_TXP3 EXP_TXN1 EXP_TXP1 VSS GCLKP VCCA_DPLLA VCC2 VCCA_EXPPLL RSV RSV VCCA_HPLL VSS VTT VTT VTT VTT HSWING HVREF HD48 VSS HD61 HD57 HD55 VSS HD53 -- Signal Name
Table 12-2. MCH Ballout Sorted By Ball Number Ball # A33 A34 A35 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 Signal Name VSS NC NC NC VSS EXP_RXP4 EXP_RXN4 VSS VSS VSS VSS VSS VSS GCLKN VSS VCCA_DPLLB VSS RSV VSS VCCA_SMPLL VSS VTT VTT VTT VTT HRCOMP VSS HD63 HDINV3# HD54 VSS HDSTBP3# HD51
Table 12-2. MCH Ballout Sorted By Ball Number Ball # B31 B32 B33 B34 B35 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 Signal Name HD52 HD15 HD13 HD11 NC VSS EXP_TXP5 VSS VSS EXP_TXN4 EXP_TXP4 EXP_TXN2 EXP_TXP2 EXP_TXN0 EXP_TXP0 VSS -- VSS RSV MTYPE NC VSS VSS VTT VTT VTT VTT VSS -- HD58 HD59 HD49 HD56
208
Intel 82925X MCH Datasheet
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Table 12-2. MCH Ballout Sorted By Ball Number Ball # C29 C30 C31 C32 C33 C34 C35 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 Signal Name HDSTBN3# HD17 HD50 HD14 HD9 HD12 VSS -- EXP_TXN5 VSS VSS EXP_RXP5 VSS VSS VSS VSS VSS VSS RSV RSV RSV VSS VSS BSEL2 VSS VTT VTT VTT VTT VSS HSCOMP VSS VSS
Table 12-2. MCH Ballout Sorted By Ball Number Ball # D27 D28 D29 D30 D31 D32 D33 D34 D35 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 Signal Name HD60 VSS HD18 VSS VSS VSS HD10 HD8 -- VSS VSS EXP_TXP6 VSS EXP_RXN5 VSS EXP_RXN3 VSS EXP_RXN2 VSS EXP_RXP0 RSV RSV RSV BSEL1 NC VSS VSS VTT VTT VTT VTT VSS HD62
Table 12-2. MCH Ballout Sorted By Ball Number Ball # E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 E35 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 Signal Name HD25 VSS HD24 HD16 VSS HBPRI# HPCREQ# HREQ1# HDSTBP0# HDINV0# HDSTBN0# EXP_TXP7 VSS EXP_TXN6 VSS VSS VSS EXP_RXP3 VSS EXP_RXP2 VSS EXP_RXN0 NC RSV RSV RSV VSS HD47 VSS HDSTBN2# VTT VTT VTT
Intel 82925X MCH Datasheet
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Table 12-2. MCH Ballout Sorted By Ball Number Ball # F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 Signal Name VSS NC VSS HDSTBN1# HD23 HD22 VSS VSS HREQ4# VSS HREQ0# HD6 VSS EXP_TXN7 VSS EXP_TXP8 VSS EXP_RXN6 EXP_RXP6 VSS VSS VSS VSS VSS NC VSS RSV VSS RSV VSS HD45 VSS VSS
Table 12-2. MCH Ballout Sorted By Ball Number Ball # G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 Signal Name VTT VTT VSS HCPURST# HD26 VSS VSS VSS HD20 HA6# HREQ3# HA7# HD7 HD5 HD3 EXP_TXP9 VSS EXP_TXN8 VSS VSS VSS EXP_RXN7 EXP_RXP7 VSS VSS EXP_RXN1 NC VSS RSV NC BSEL0 NC HD46
Table 12-2. MCH Ballout Sorted By Ball Number Ball # H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 H35 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 Signal Name HD41 HD40 VSS VTT HD37 VSS VSS HDSTBP1# VSS HD19 HA3# VSS HREQ2# VSS HD1 VSS HD4 EXP_TXN9 VSS EXP_TXP10 VSS EXP_RXN8 EXP_RXP8 VSS VSS VSS VSS EXP_RXP1 NC RSV RSV VSS VSS
210
Intel 82925X MCH Datasheet
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Ballout and Package Information
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Table 12-2. MCH Ballout Sorted By Ball Number Ball # J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J31 J32 J33 J34 J35 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 Signal Name VSS VSS HDSTBP2# VSS HD35 HD32 VSS HD33 HD27 HDINV1# HD21 HA13# HA5# VSS HADSTB0# HRS2# HD0 HD2 HDEFER# EXP_TXP11 VSS EXP_TXN10 VSS VSS VSS EXP_RXN9 EXP_RXP9 VSS VSS VSS NC RSV VSS
Table 12-2. MCH Ballout Sorted By Ball Number Ball # K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 K31 K32 K33 K34 K35 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 Signal Name RSV EXTTS# HD44 HD43 HDINV2# VSS HD39 HD34 HD31 VSS HD28 VSS HA14# VSS HA4# HA8# VSS VSS HA15# HRS0# VSS EXP_TXN11 VSS EXP_TXP12 VSS EXP_RXN10 EXP_RXP10 VSS VSS VSS VCC VSS NC
Table 12-2. MCH Ballout Sorted By Ball Number Ball # L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 L27 L28 L29 L30 L31 L32 L33 L34 L35 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 Signal Name VSS RSV VSS VSS VSS VSS NC VSS VSS VSS HD30 VSS HD29 HA18# VSS HA12# HA9# VSS HA11# VSS HLOCK# HHIT# HDBSY# EXP_TXP13 VSS EXP_TXN12 VSS VSS VSS EXP_RXN12 EXP_RXP12 VSS VSS
Intel 82925X MCH Datasheet
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Table 12-2. MCH Ballout Sorted By Ball Number Ball # M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25 M26 M27 M28 M29 M30 M31 M32 M33 M34 M35 N1 N2 N3 N4 N5 N6 N7 N8 Signal Name VSS DREFCLKN DREFCLKP ICH_SYNC# RSV RSV VSS HD42 HD38 VSS HD36 HCLKN HCLKP VSS VSS HA20# VSS HA16# VSS HA10# HADS# HDRDY# -- VSS HBNR# EXP_TXN13 VSS EXP_TXP14 VSS EXP_RXN13 EXP_RXP13 VSS VSS
Table 12-2. MCH Ballout Sorted By Ball Number Ball # N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 N26 N27 N28 N29 N30 N31 N32 N33 N34 N35 P1 P2 P3 P4 P5 P6 Signal Name VSS VSS VSS NC VCC VCC VCC VCC VSS VCC VSS VCC VCC NC NC NC VSS HA19# HADSTB1# VSS HA23# VSS HA21# VSS HA26# HTRDY# HHITM# EXP_TXP15 VSS EXP_TXN14 VSS VSS VSS
Table 12-2. MCH Ballout Sorted By Ball Number Ball # P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 R1 R2 R3 R4 Signal Name EXP_RXP14 EXP_RXN14 VSS EXP_RXP11 VSS NC VCC VCC VCC VSS VCC VSS VCC VSS VCC VCC NC NC VSS HA22# VSS HA24# VSS NC VSS VSS HEDRDY# HRS1# VSS EXP_TXN15 VSS DMI_TXP0 VSS
212
Intel 82925X MCH Datasheet
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Ballout and Package Information
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Table 12-2. MCH Ballout Sorted By Ball Number Ball # R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 T1 T2 Signal Name EXP_RXN15 EXP_RXP15 VSS VSS VSS EXP_RXN11 VSS NC VCC VCC VCC VCC VSS VCC VSS VCC VSS VCC VCC NC VSS VSS VSS HA25# HA17# SCB_A4 SCB_A5 SDQ_A58 HBREQ0# SDQ_A59 RSV DMI_TXP1 VSS
Table 12-2. MCH Ballout Sorted By Ball Number Ball # T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 Signal Name DMI_TXN0 VSS VSS VSS VSS DMI_RXN1 DMI_RXP1 VSS VSS NC VCC VCC VCC VCC VCC VSS VCC VCC VCC VSS VCC VCC VSS HA30# HA27# VSS HA31# VSS HA28# VSS SDQ_A62 VSS SDQ_A63
Table 12-2. MCH Ballout Sorted By Ball Number Ball # U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 U26 U27 U28 U29 U30 U31 U32 U33 Signal Name DMI_TXN1 VSS DMI_TXP2 VSS DMI_RXP0 DMI_RXN0 VSS VSS VSS DMI_RXN3 VSS NC VCC VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS SDQ_B63 VSS HA29# VSS SDQS_A8# VSS VSS SDM_A7
Intel 82925X MCH Datasheet
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Table 12-2. MCH Ballout Sorted By Ball Number Ball # U34 U35 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31 Signal Name SDQS_A7 SDQS_A7# VSS VSS DMI_TXN2 VSS DMI_TXP3 VSS DMI_RXP2 DMI_RXN2 VSS DMI_RXP3 VSS NC VCC VCC VCC VSS VCC VSS VCC VSS VCC VSS VCC VCC VSS VSS VSS SDQ_B58 SDQ_B59 SDQS_A8 SCB_A1
Table 12-2. MCH Ballout Sorted By Ball Number Ball # V32 V33 V34 V35 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 W27 W28 W29 Signal Name SCB_A0 SDQ_A57 SDQ_A56 VSS VCC_EXP VCC_EXP VCC_EXP VCC_EXP DMI_TXN3 VCC_EXP VCC_EXP VCC_EXP VCC_EXP EXP_COMPI VSS NC VCC VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS SDQ_B62 SDQS_B7 VSS SDQ_B57
Table 12-2. MCH Ballout Sorted By Ball Number Ball # W30 W31 W32 W33 W34 W35 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 Y27 Signal Name VSS SDM_B7 VSS SDQ_A61 SDQ_A51 SDQ_A60 VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP EXP_COMPO VSS NC VCC VCC VCC VCC VCC VSS VCC VCC VCC VSS VCC VCC VSS SDQ_B60 VSS
214
Intel 82925X MCH Datasheet
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Table 12-2. MCH Ballout Sorted By Ball Number Ball # Y28 Y29 Y30 Y31 Y32 Y33 Y34 Y35 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 Signal Name SDQS_B7# VSS SCB_A6 VSS VSS SDQ_A50 VSS SDQ_A55 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC VCC VCC VSS VCC VSS VCC VSS VCC VCC VCC VCC VCC VSS
Table 12-2. MCH Ballout Sorted By Ball Number Ball # AA26 AA27 AA28 AA29 AA30 AA31 AA32 AA33 AA34 AA35 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 Signal Name VSS VSS SDQ_B56 SDQ_B61 SCB_A3 SCB_A2 SDQ_A54 SDM_A6 SDQS_A6 SDQS_A6# VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC NC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
Table 12-2. MCH Ballout Sorted By Ball Number Ball # AB24 AB25 AB26 AB27 AB28 AB29 AB30 AB31 AB32 AB33 AB34 AB35 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 Signal Name VCC VSS SDQ_B51 SDQ_B55 VSS SCB_A7 VSS SDQS_B6 VSS RSV SCLK_A5# VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV
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Table 12-2. MCH Ballout Sorted By Ball Number Ball # AC22 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC30 AC31 AC32 AC33 AC34 AC35 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 Signal Name RSV NC NC VSS SDQ_B50 VSS SDQ_B54 VSS SDQS_B6# VSS VSS SCLK_A5 SCLK_A2 SCLK_A2# VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VSS SDQ_B20 VSS SDQ_B17 SDQ_B29 VSS SDQ_A29 SDQ_B24 VSS
Table 12-2. MCH Ballout Sorted By Ball Number Ball # AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 AD32 AD33 AD34 AD35 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 Signal Name VSS NC VSS SDQ_B37 SDM_B6 VSS VSS SDQ_A35 SCLK_B5 SCLK_B5# NC SDQ_A48 RSV -- VSS SDQ_A49 SDQ_A5 SDQ_A4 SDQ_A0 VSS SOCOMP1 VSS SVREF0 SVREF1 VSS SM_SLEWOUT1 SDQ_B4 VSS SDQ_B21 SDQ_B19 SDQ_A28 RSV_TP0 SDQ_A24
Table 12-2. MCH Ballout Sorted By Ball Number Ball # AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27 AE28 AE29 AE30 AE31 AE32 AE33 AE34 AE35 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 NC SDQ_B25 SDM_B3 VSS VSS VSS VSS SCLK_B2# SCLK_B2 SDQ_B49 VSS SDQ_B53 NC SDQ_B52 VSS SDQ_A43 SDQ_A53 SDQ_A52 VSS SDM_A0 SDQ_A1 VSS SOCOMP0 VSS RSTIN# VSS SM_SLEWIN1 VSS SDQ_B5 SDQ_B11 SDQ_B16 SDQ_B18 SDQ_B28 Signal Name
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Table 12-2. MCH Ballout Sorted By Ball Number Ball # AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AF30 AF31 AF32 AF33 AF34 AF35 AG1 AG2 AG3 AG4 AG5 AG6 AG7 AG8 AG9 AG10 AG11 AG12 AG13 Signal Name SDQ_A25 SDM_A3 VSS NC SDQS_B3# VSS NC SDQ_B36 SDQ_B32 SDM_B4 VSS SDQ_B48 SDQ_A39 VSS SDQ_B43 VSS VSS SDQ_A42 SDQ_A47 VSS SDQS_A0 SDQS_A0# SDQ_A6 SRCOMP0 VSS NC PWROK SRCOMP1 VSS SDQ_B1 SDQ_B0 VSS VSS
Table 12-2. MCH Ballout Sorted By Ball Number Ball # AG14 AG15 AG16 AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29 AG30 AG31 AG32 AG33 AG34 AG35 AH1 AH2 AH3 AH4 AH5 AH6 AH7 AH8 AH9 AH10 AH11 Signal Name SDQS_B2# VSS VSS SDQS_A3# VSS VSS SDQS_B3 VSS VSS SCLK_B0# SDQ_B33 NC SDQS_B4# SDQ_A38 SDQ_B47 NC SDQ_B46 SDQ_B42 SDQ_A46 SDQS_A5# SDM_A5 SDQS_A5 VSS SDQ_A7 SDQ_A2 SDQ_B12 NC VSS SDQ_B7 SDQS_B0 SDQS_B0# SDM_B0 VSS
Table 12-2. MCH Ballout Sorted By Ball Number Ball # AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29 AH30 AH31 AH32 AH33 AH34 AH35 AJ1 AJ2 AJ3 AJ4 AJ5 AJ6 AJ7 AJ8 AJ9 Signal Name SDM_B2 SDQS_B2 VSS RSV_TP1 SDQS_A3 SDQ_A27 VSS SDQ_B30 VSS SDQ_B31 VSS SCLK_B0 NC SDQS_B4 VSS SDQ_A34 SDQS_B5 VSS SDQS_B5# SDM_B5 VSS VSS SDQ_A40 SDQ_A41 SDQ_A12 SDQ_A3 SDQ_A13 VSS SDQ_B13 SDQ_B3 SDQ_B2 SDQ_B6 VSS
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Table 12-2. MCH Ballout Sorted By Ball Number Ball # AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AJ31 AJ32 AJ33 AJ34 AJ35 AK1 AK2 AK3 AK4 AK5 AK6 AK7 Signal Name VSS SCLK_B4 SM_SLEWIN0 VSS NC VSS VSS SDQ_A31 SCB_B1 VSS SCB_B0 SDQS_B8# VSS SCB_B2 SCB_B3 SDQ_B39 SDQ_B35 VSS SDQS_A4# SDQ_B44 VSS SDQ_B41 VSS SDM_A4 SDQ_A45 VSS VSS SDQ_A8 SDQ_A9 VSS SDM_B1 VSS SDQ_A17
Table 12-2. MCH Ballout Sorted By Ball Number Ball # AK8 AK9 AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17 AK18 AK19 AK20 AK21 AK22 AK23 AK24 AK25 AK26 AK27 AK28 AK29 AK30 AK31 AK32 AK33 AK34 AK35 AL1 AL2 AL3 AL4 AL5 Signal Name VSS SCLK_B1 SDQ_B8 VSS SM_SLEWOUT0 SDQ_B22 VSS RSV_TP3 SDQ_A30 VSS SCB_B5 SDQ_B27 VSS SDQS_B8 SCLK_B3# VSS NC VSS VSS SDQS_A4 SCLK_A3# SDQ_A32 VSS SDQ_A33 SDQ_B40 SDQ_B45 SDQ_A44 VCCSM SDM_A1 SDQS_A1# SDQS_A1 SDQ_B9 SDQS_B1#
Table 12-2. MCH Ballout Sorted By Ball Number Ball # AL6 AL7 AL8 AL9 AL10 AL11 AL12 AL13 AL14 AL15 AL16 AL17 AL18 AL19 AL20 AL21 AL22 AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL30 AL31 AL32 AL33 AL34 AL35 AM1 AM2 AM3 Signal Name SDQ_B14 SDQ_A19 SDQ_B10 SCLK_B1# VSS SCLK_B4# VCCSM VSS SDQ_B23 RSV_TP2 VSS SDQ_A26 SDQ_B26 VSS SCB_B4 SCB_B6 SCB_B7 SCLK_B3 VSS SDQ_B38 SDQ_B34 NC SCLK_A3 SCLK_A0 SDQ_A36 SDQ_A37 VSS SODT_B3 SODT_B1 SODT_B2 -- SCLK_A4# SCLK_A4
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Table 12-2. MCH Ballout Sorted By Ball Number Ball # AM4 AM5 AM6 AM7 AM8 AM9 AM10 AM11 AM12 AM13 AM14 AM15 AM16 AM17 AM18 AM19 AM20 AM21 AM22 AM23 AM24 AM25 AM26 AM27 AM28 AM29 AM30 AM31 AM32 AM33 AM34 AM35 AN1 Signal Name VSS SDQS_B1 VSS SDQ_A22 SDQ_A23 SDQ_A18 VCCSM VCCSM NC VCCSM VCCSM NC VCCSM VCCSM NC VCCSM VCCSM NC VCCSM VCCSM NC VCCSM VCCSM VCCSM VSS VCCSM SCLK_A0# VSS VCCSM SCS_B1# SMA_B13 -- VSS
Table 12-2. MCH Ballout Sorted By Ball Number Ball # AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 AN32 AN33 AN34 Signal Name SCLK_A1 SCLK_A1# SDQ_A10 SDQ_A21 SDQ_B15 SDQS_A2# SCKE_B3 SBS_B2 SMA_B12 SMA_B5 -- SMA_B4 SMA_B2 SMA_B0 SBS_B1 SRAS_B# SCKE_A2 SCKE_A1 SMA_A12 SMA_A7 SMA_A5 SMA_A8 -- SMA_A2 SMA_A0 SBS_A0 SWE_A# SODT_A2 SMA_A13 SCS_A1# SODT_A3 SCS_B2# SODT_B0
Table 12-2. MCH Ballout Sorted By Ball Number Ball # AN35 AP1 AP2 AP3 AP4 AP5 AP6 AP7 AP8 AP9 AP10 AP11 AP12 AP13 AP14 AP15 AP16 AP17 AP18 AP19 AP20 AP21 AP22 AP23 AP24 AP25 AP26 AP27 AP28 AP29 AP30 AP31 AP32 Signal Name VCCSM NC SDQ_A14 SDQ_A15 SDQ_A11 SDQ_A16 SDM_A2 SDQS_A2 VCCSM SCKE_B1 SMA_B11 SMA_B9 VCCSM SMA_B6 SMA_B3 SMA_B10 VCCSM SWE_B# SCAS_B# SCKE_A0 VCCSM SMA_A11 SMA_A9 SMA_A4 VCCSM SMA_A1 SMA_A10 SRAS_A# VCCSM SCAS_A# SODT_A0 SCS_A3# SODT_A1
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Table 12-2. MCH Ballout Sorted By Ball Number Ball # AP33 AP34 AP35 AR1 AR2 AR3 AR4 AR5 AR6 AR7 AR8 AR9 AR10 Signal Name SCS_B0# SCS_B3# NC NC NC VSS -- SDQ_A20 VSS VCCSM SCKE_B2 SCKE_B0 VCCSM
Table 12-2. MCH Ballout Sorted By Ball Number Ball # AR11 AR12 AR13 AR14 AR15 AR16 AR17 AR18 AR19 AR20 AR21 AR22 AR23 Signal Name SMA_B7 SMA_B8 VSS VCCSM SMA_B1 SBS_B0 VSS VCCSM SCKE_A3 SBS_A2 VSS VCCSM SMA_A6
Table 12-2. MCH Ballout Sorted By Ball Number Ball # AR24 AR25 AR26 AR27 AR28 AR29 AR30 AR31 AR32 AR33 AR34 AR35 Signal Name SMA_A3 VSS VCCSM SBS_A1 SCS_A2# SCS_A0# VSS VCCSM -- VCCSM NC NC
12.2
Package Information
The MCH package measures 37.5 mm x 37.5 mm. The 1210 balls are located in a non-grid pattern. For example, the ball pitch varies from 31.8 mils to 43.0 mils, depending on the X-axis or Y-axis direction. Figure 12-3 shows the physical dimensions of the package and Error! Reference source not found. shows the MCH keep-out regions.
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Figure 12-3. MCH Package Dimensions
MCH
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13
Testability
In the 82925X MCH, testability for Automated Test Equipment (ATE) board level testing has been implemented as an XOR chain. An XOR-tree is a chain of XOR gates each with one input pin connected to it.
13.1
Complimentary Pins
Table 13-1 contains pins which must remain complimentary while performing XOR testing. The first and third columns contain the pin and its compliment. The second and fourth columns specify which chain the associated pins are on. Note: In non ECC systems, SDQS_A8, SDQS_A8#, SDQS_B8 and SDQS_B8# do not need to be driven.
Table 13-1. Complimentary Pins to Drive
Complimentary Pin SDQS_A0 SDQS_A1 SDQS_A2 SDQS_A3 SDQS_A4 SDQS_A5 SDQS_A6 SDQS_A7 SDQS_A8 SDQS_B0 SDQS_B1 SDQS_B2 SDQS_B3 SDQS_B4 SDQS_B5 SDQS_B6 SDQS_B7 SDQS_B8 XOR Chain SM XOR 6 SM XOR 6 SM XOR 6 SM XOR 4 SM XOR 4 SM XOR 2 SM XOR 2 SM XOR 2 SM XOR 2 SM XOR 7 SM XOR 7 SM XOR 7 SM XOR 7 SM XOR 7 SM XOR 3 SM XOR 3 SM XOR 3 SM XOR 7 Complimentary Pin SDQS_A0# SDQS_A1# SDQS_A2# SDQS_A3# SDQS_A4# SDQS_A5# SDQS_A6# SDQS_A7# SDQS_A8# SDQS_B0# SDQS_B1# SDQS_B2# SDQS_B3# SDQS_B4# SDQS_B5# SDQS_B6# SDQS_B7# SDQS_B8# XOR Chain SM XOR 4 SM XOR 4 SM XOR 4 SM XOR 6 SM XOR 2 SM XOR 4 SM XOR 4 SM XOR 4 SM XOR 4 SM XOR 5 SM XOR 5 SM XOR 5 SM XOR 5 SM XOR 5 SM XOR 5 SM XOR 5 SM XOR 5 SM XOR 5
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13.2
XOR Test Mode Initialization
XOR test mode can be entered by pulling reserved ballout RSV (located at F15) and MTYPE low through the de-assertion of external reset (RSTIN#). It is recommended that customers use the following sequence. After power up, hold PWROK, PCIRST#, and reserved ballout RSV (located at F15) and MTYPE low and start external clocks. After 20 cycles, pull PWROK high. After 15 clocks, de-assert PCIRST# (pull it high). Release reserved ballout RSV (located at F15) and MTYPE. No external drive. Allow the clocks to run for an additional 32 clocks. Begin testing the XOR chains.
13.3
XOR Chain Definition
The 82925X MCH has 10 XOR chains. The XOR chain outputs are driven out on the following output pins. During full-width testing, XOR chain outputs will be visible on both pins. For example xor_out0 will be visible on BSEL2.
Table 13-2. XOR Chain Outputs
XOR Chain xor_out0 xor_out1 xor_out2 xor_out3 xor_out4 xor_out5 xor_out6 xor_out7 xor_out8 xor_out9 Output Pins BSEL2 RSV RSV MTYPE RSV RSV RSV RSV BSEL1 BSEL0 Coordinate Location D17 M16 F15 C15 A16 B15 C14 K15 E15 H16
13.4
XOR Chains
The following tables show the XOR chains. The last section in this chapter has a pin exclusion list. The chain files are golden, if there is a pin missing from the chain files and exclusion list, it should be added to the exclusion list.
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Table 13-3. XOR Chain #0
Chain 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Pin Count 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Ball Number M14 K16 G24 K17 M18 K18 F17 M19 K21 K19 H18 J19 F19 G18 K22 M21 J21 H20 H19 J24 J22 H23 A25 A29 D27 B26 B29 C29 C25 B30 E27 C30 E25 H28 Signal Name ICH_SYNC# EXTTS# HCPURST# HD44 HD42 HD43 HD47 HD38 HD39 HDINV2# HD46 HDSTBP2# HDSTBN2# HD45 HD34 HD36 HD35 HD40 HD41 HD33 HD32 HD37 HD48 HD55 HD60 HDINV3# HDSTBP3# HDSTBN3# HD58 HD51 HD24 HD17 HD25 HD19
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Chain 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XOR Chain #0 Output
Pin Count 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65
Ball Number F27 F28 H26 F26 J27 J25 K25 K23 L23 J26 G25 L25 B32 G33 H33 H35 J34 G30 H29 J28 J29 K33 F31 K29 L31 K27 M30 F33 E30 J35 P33 D17
Signal Name HD23 HD22 HDSTBP1# HDSTBN1# HD21 HD27 HD28 HD31 HD30 HDINV1# HD26 HD29 HD15 HD7 HD1 HD4 HD2 HA6# HA3# HA13# HA5# HA15# HREQ4# HA4# HA11# HA14# HA10# HREQ0# HBPRI# HDEFER# HEDRDY# BSEL2
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Table 13-4. XOR Chain #1
Chain 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Pin Count 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Ball Number A28 A27 B27 B25 E24 C26 C27 C28 A31 C31 B31 D29 E28 G29 B34 B33 C32 C33 C34 D34 D33 E34 E33 E35 F34 G34 G35 J33 G32 H31 K30 J31 G31 E31 Signal Name HD57 HD61 HD54 HD63 HD62 HD59 HD49 HD56 HD53 HD50 HD52 HD18 HD16 HD20 HD11 HD13 HD14 HD9 HD12 HD8 HD10 HDINV0# HDSTBP0# HDSTBN0# HD6 HD5 HD3 HD0 HA7# HREQ2# HA8# HADSTB0# HREQ3# HPCREQ#
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Chain 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 XOR Chain #1 Output
Pin Count 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66
Ball Number L29 L28 J32 K34 L33 M32 M31 L34 M35 L35 N35 P34 N34 R33 N31 N33 T31 E32 T27 M26 N26 P28 U28 N27 L26 M28 T29 R28 N29 T26 P26 R29 M16
Signal Name HA9# HA12# HRS2# HRS0# HLOCK# HDRDY# HADS# HHIT# HBNR# HDBSY# HHITM# HRS1# HTRDY# HBREQ0# HA21# HA26# HA28# HREQ1# HA27# HA20# HA19# HA24# HA29# HADSTB1# HA18# HA16# HA31# HA25# HA23# HA30# HA22# HA17# RSV_M16
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Table 13-5. XOR Chain #2
Chain 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Pin Count 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Ball Number R32 R34 T35 W35 T33 V34 V33 U33 W33 U34 V30 AA31 AA30 Y30 AB29 V31 V32 R31 R30 AA34 W34 Y35 Y33 AD35 AE35 AE34 AA33 AA32 AD31 AC35 AB34 AC33 AF34 AH35 Signal Name SDQ_A58 SDQ_A59 SDQ_A63 SDQ_A60 SDQ_A62 SDQ_A56 SDQ_A57 SDM_A7 SDQ_A61 SDQS_A7 SDQS_A8 SCB_A2 SCB_A3 SCB_A6 SCB_A7 SCB_A1 SCB_A0 SCB_A5 SCB_A4 SDQS_A6 SDQ_A51 SDQ_A55 SDQ_A50 SDQ_A49 SDQ_A52 SDQ_A53 SDM_A6 SDQ_A54 SDQ_A48 SCLK_A2# SCLK_A5# SCLK_A5 SDQ_A47 SDQ_A41
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Chain 2 2 2 2 2 2 2 2 2 2 2 2 2 2 XOR Chain #2 Output
Pin Count 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Ball Number AJ34 AG34 AE33 AF33 AG32 AH34 AK34 AG35 AR29 AN32 AN29 AP32 AP30 AJ28 F15
Signal Name SDQ_A45 SDM_A5 SDQ_A43 SDQ_A42 SDQ_A46 SDQ_A40 SDQ_A44 SDQS_A5 SCS_A0# SODT_A3 SODT_A2 SODT_A1 SODT_A0 SDQS_A4# RSV_F15
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Table 13-6. XOR Chain #3
Chain 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Pin Count 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Ball Number W26 U26 V28 V29 W29 W31 AA29 AA28 Y26 W27 AB31 AB27 AE31 AC26 AE27 AE29 AF27 AB26 AC28 AD24 AN33 AD29 AE25 AE26 AP34 AP33 AM33 AL33 AL34 AL35 AN34 AF30 AK32 AH31 Signal Name SDQ_B62 SDQ_B63 SDQ_B58 SDQ_B59 SDQ_B57 SDM_B7 SDQ_B61 SDQ_B56 SDQ_B60 SDQS_B7 SDQS_B6 SDQ_B55 SDQ_B52 SDQ_B50 SDQ_B49 SDQ_B53 SDQ_B48 SDQ_B51 SDQ_B54 SDM_B6 SCS_B2# SCLK_B5# SCLK_B2# SCLK_B2 SCS_B3# SCS_B0# SCS_B1# SODT_B3 SODT_B1 SODT_B2 SODT_B0 SDQ_B43 SDQ_B40 SDM_B5
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Chain 3 3 3 3 3 3 3 3 3 3 3 3 3 XOR Chain #3 Output
Pin Count 35 36 37 38 39 40 41 42 43 44 45 46 47
Ball Number AK33 AJ31 AG28 AJ29 AG31 AH28 AM34 AJ25 AL25 AJ26 AL26 AF23 AG24 C15
Signal Name SDQ_B45 SDQ_B41 SDQ_B47 SDQ_B44 SDQ_B42 SDQS_B5 SMA_B13 SDQ_B39 SDQ_B38 SDQ_B35 SDQ_B34 SDQ_B36 SDQ_B33 MTYPE
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Table 13-7. XOR Chain #4
Chain 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Pin Count 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Ball Number U35 U30 AA35 AC34 AG33 AN31 AP31 AK27 AD27 AL30 AJ33 AK31 AF28 AH27 AG27 AL31 AK29 AP29 AN28 AR28 AR27 AP27 AN27 AM30 AL29 AL28 AK28 AN25 AP26 AN26 AN30 AP25 AP23 AR24 Signal Name SDQS_A7# SDQS_A8# SDQS_A6# SCLK_A2 SDQS_A5# SCS_A1# SCS_A3# SDQS_A4 SDQ_A35 SDQ_A36 SDM_A4 SDQ_A33 SDQ_A39 SDQ_A34 SDQ_A38 SDQ_A37 SDQ_A32 SCAS_A# SWE_A# SCS_A2# SBS_A1 SRAS_A# SBS_A0 SCLK_A0# SCLK_A0 SCLK_A3 SCLK_A3# SMA_A2 SMA_A10 SMA_A0 SMA_A13 SMA_A1 SMA_A4 SMA_A3
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Chain 4 4 4 4 4 4 4 4 4 4 4 4 4 XOR Chain #4 Output
Pin Count 35 36 37 38 39 40 41 42 43 44 45 46 47
Ball Number AR23 AN23 AH16 AH17 AL17 AF16 AE17 AD17 AN18 AN7 AN3 AL2 AG2 A16
Signal Name SMA_A6 SMA_A8 SDQS_A3 SDQ_A27 SDQ_A26 SDQ_A25 SDQ_A24 SDQ_A29 SCKE_A2 SDQS_A2# SCLK_A1# SDQS_A1# SDQS_A0# RSV_A16
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Table 13-8. XOR Chain #5
Chain 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Pin Count 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Ball Number Y28 AC30 AD28 AG30 AH30 AF25 AD23 AF24 AG26 AF20 AH19 AD15 AD18 AE20 AK19 AH21 AL18 AF15 AE19 AK22 AG23 AH23 AL21 AK18 AJ23 AB29 AJ24 AL20 AJ20 AJ18 AJ21 AN17 AP18 AP17 Signal Name SDQS_B7# SDQS_B6# SCLK_B5 SDQ_B46 SDQS_B5# SDM_B4 SDQ_B37 SDQ_B32 SDQS_B4# SDQS_B3# SDQ_B30 SDQ_B29 SDQ_B24 SDM_B3 SDQ_B27 SDQ_B31 SDQ_B26 SDQ_B28 SDQ_B25 SCLK_B3# SCLK_B0# SCLK_B0 SCB_B6 SCB_B5 SCB_B2 SCB_A7 SCB_B3 SCB_B4 SCB_B0 SCB_B1 SDQS_B8# SRAS_B# SCAS_B# SWE_B#
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Chain 5 5 5 5 5 5 5 5 5 5 5 5 5 XOR Chain #5 Output
Pin Count 35 36 37 38 39 40 41 42 43 44 45 46 47
Ball Number AR16 AN16 AN14 AN15 AP15 AR15 AP14 AN13 AR9 AG14 AL9 AL5 AH9 B15
Signal Name SBS_B0 SBS_B1 SMA_B2 SMA_B0 SMA_B10 SMA_B1 SMA_B3 SMA_B4 SCKE_B0 SDQS_B2# SCLK_B1# SDQS_B1# SDQS_B0# RSV_B15
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Table 13-9. XOR Chain #6
Chain 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Pin Count 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Ball Number AG17 AF17 AJ17 AK16 AE15 AN19 AP21 AP22 AN22 AR20 AN21 AN20 AP19 AR19 AP7 AM9 AL7 AM8 AM7 AP6 AK7 AP5 AN5 AR5 AM2 AM3 AN2 AP4 AP3 AP2 AN4 AK3 AK2 AJ3 Signal Name SDQS_A3# SDM_A3 SDQ_A31 SDQ_A30 SDQ_A28 SCKE_A1 SMA_A11 SMA_A9 SMA_A5 SBS_A2 SMA_A7 SMA_A12 SCKE_A0 SCKE_A3 SDQS_A2 SDQ_A18 SDQ_A19 SDQ_A23 SDQ_A22 SDM_A2 SDQ_A17 SDQ_A16 SDQ_A21 SDQ_A20 SCLK_A4# SCLK_A4 SCLK_A1 SDQ_A11 SDQ_A15 SDQ_A14 SDQ_A10 SDQ_A9 SDQ_A8 SDQ_A13
236
Intel 82925X MCH Datasheet
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Testability
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Chain 6 6 6 6 6 6 6 6 6 6 6 6 6 XOR Chain #6 Output
Pin Count 35 36 37 38 39 40 41 42 43 44 45 46 47
Ball Number AJ1 AL1 AL3 AG1 AG3 AF2 AH2 AH3 AJ2 AF3 AE3 AE2 AE1 C14
Signal Name SDQ_A12 SDM_A1 SDQS_A1 SDQS_A0 SDQ_A6 SDM_A0 SDQ_A7 SDQ_A2 SDQ_A3 SDQ_A1 SDQ_A0 SDQ_A4 SDQ_A5 RSV_C14
Intel 82925X MCH Datasheet
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237
Testability
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Table 13-10. XOR Chain #7
Chain 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Pin Count 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Ball Number AH25 AG20 AL23 AK21 AP13 AP11 AR12 AR11 AN10 AP10 AN9 AN11 AR8 AP9 AN8 AE14 AF14 AK13 AH12 AD14 AL14 AD12 AF13 AE13 AH13 AL11 AJ11 AK9 AL4 AJ5 AH4 AK10 AL8 AN6 Signal Name SDQS_B4 SDQS_B3 SCLK_B3 SDQS_B8 SMA_B6 SMA_B9 SMA_B8 SMA_B7 SMA_B12 SMA_B11 SBS_B2 SMA_B5 SCKE_B2 SCKE_B1 SCKE_B3 SDQ_B19 SDQ_B18 SDQ_B22 SDM_B2 SDQ_B17 SDQ_B23 SDQ_B20 SDQ_B16 SDQ_B21 SDQS_B2 SCLK_B4# SCLK_B4 SCLK_B1 SDQ_B9 SDQ_B13 SDQ_B12 SDQ_B8 SDQ_B10 SDQ_B15
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Intel 82925X MCH Datasheet
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Testability
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Chain 7 7 7 7 7 7 7 7 7 7 7 7 7 7 XOR Chain #7 Output
Pin Count 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Ball Number AL6 AK5 AF12 AM5 AH8 AE11 AF11 AG10 AJ7 AJ6 AJ8 AH10 AG11 AH7 K15
Signal Name SDQ_B14 SDM_B1 SDQ_B11 SDQS_B1 SDQS_B0 SDQ_B4 SDQ_B5 SDQ_B1 SDQ_B2 SDQ_B3 SDQ_B6 SDM_B0 SDQ_B0 SDQ_B7 RSV_K15
Intel 82925X MCH Datasheet
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239
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Table 13-11. XOR Chain #8
Chain 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Pin Count 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Ball Number F11 C9 H11 A8 E9 C7 E7 A6 B4 C5 E5 D2 G5 F3 H7 G1 J5 H3 K7 J1 L5 K3 R10 L1 M7 M3 N5 N1 P8 P3 R5 R1 E11 C10 Signal Name EXP_RXN0 EXP_TXN0 EXP_RXN1 EXP_TXN1 EXP_RXN2 EXP_TXN2 EXP_RXN3 EXP_TXN3 EXP_RXN4 EXP_TXN4 EXP_RXN5 EXP_TXN5 EXP_RXN6 EXP_TXN6 EXP_RXN7 EXP_TXN7 EXP_RXN8 EXP_TXN8 EXP_RXN9 EXP_TXN9 EXP_RXN10 EXP_TXN10 EXP_RXN11 EXP_TXN11 EXP_RXN12 EXP_TXN12 EXP_RXN13 EXP_TXN13 EXP_RXN14 EXP_TXN14 EXP_RXN15 EXP_TXN15 EXP_RXP0 EXP_TXP0
240
Intel 82925X MCH Datasheet
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Testability
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Chain 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 XOR Chain #8 Output
Pin Count 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Ball Number J11 A9 F9 C8 F7 A7 B3 C6 D5 C2 G6 E3 H8 F1 J6 G3 K8 H1 L6 J3 P10 K1 M8 L3 N6 M1 P7 N3 R6 P1 E15
Signal Name EXP_RXP1 EXP_TXP1 EXP_RXP2 EXP_TXP2 EXP_RXP3 EXP_TXP3 EXP_RXP4 EXP_TXP4 EXP_RXP5 EXP_TXP5 EXP_RXP6 EXP_TXP6 EXP_RXP7 EXP_TXP7 EXP_RXP8 EXP_TXP8 EXP_RXP9 EXP_TXP9 EXP_RXP10 EXP_TXP10 EXP_RXP11 EXP_TXP11 EXP_RXP12 EXP_TXP12 EXP_RXP13 EXP_TXP13 EXP_RXP14 EXP_TXP14 EXP_RXP15 EXP_TXP15 BSEL1
Intel 82925X MCH Datasheet
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241
Testability
R
Table 13-12. XOR Chain #9
Chain 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 XOR Chain #9 Output Pin Count 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Ball Number U6 U5 T3 R3 T8 T9 U1 T1 V8 V7 V3 U3 U10 V10 W5 V5 H16 Signal Name DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0 DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1 DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2 DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3 BSEL0
242
Intel 82925X MCH Datasheet
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13.5
Pads Excluded from XOR Mode(s)
A large number of pads do not support XOR testing. The majority of the pads that fall into this category are analog related pins. refer to the Table 13-13.
Table 13-13. XOR Pad Exclusion List
3GIO GCLKN GCLKP EXP_COMPO EXP_COMPI FSB HCLKN HCLKP HRCOMP HSCOMP HVREF HSWING SM SRCOMP1 SRCOMP0 SMVREF1 SMVREF0 SOCOMP1 SOCOMP0 SM_SLEWOUT1 SM_SLEWOUT0 SM_SLEWIN1 SM_SLEWIN0 Misc DREFCLKN DREFCLKP BLUE BLUE# GREEN GREEN# RED RED# RSTIN# HSYNC VSYNC REFSET
Intel 82925X MCH Datasheet
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243

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